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/Zephyr-Core-3.7.0/boards/enjoydigital/litex_vexriscv/
Dlitex_vexriscv.dts83 &clk1 {
/Zephyr-Core-3.7.0/samples/drivers/clock_control_litex/
DREADME.rst31 :start-at: clk1: clock-controller@1 {
41 This configuration defines 2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100…
43 **Important note:** ``reg`` properties in ``clk0`` and ``clk1`` nodes reference the clock output n…
/Zephyr-Core-3.7.0/tests/net/ptp/clock/src/
Dmain.c485 static ZTEST_BMEM const struct device *clk1; variable
509 clk1 = clk; in test_ptp_clock_get_by_index()
527 zassert_equal(clk1, clk_by_index, "Invalid PTP clock 1"); in test_ptp_clock_get_by_index_user()
/Zephyr-Core-3.7.0/dts/riscv/
Driscv32-litex-vexriscv.dtsi308 clk1: clock-controller@1 { label
341 clocks = <&clk0 0>, <&clk1 1>;