Searched refs:clk0 (Results 1 – 4 of 4) sorted by relevance
25 :start-at: clk0: clock-controller@0 {41 This configuration defines 2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100…43 **Important note:** ``reg`` properties in ``clk0`` and ``clk1`` nodes reference the clock output n…54 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
79 &clk0 {
484 static ZTEST_BMEM const struct device *clk0; variable497 clk0 = clk; in test_ptp_clock_get_by_index()523 zassert_equal(clk0, clk_by_index, "Invalid PTP clock 0"); in test_ptp_clock_get_by_index_user()540 zassert_equal(clk0, clk_by_index, "Invalid PTP clock 0 (%s)", who); in test_ptp_clock_get_by_xxx()
295 clk0: clock-controller@0 { label341 clocks = <&clk0 0>, <&clk1 1>;
