| /Zephyr-Core-3.7.0/subsys/modbus/ |
| D | modbus_serial.c | 34 struct modbus_serial_config *cfg = ctx->cfg; in modbus_serial_tx_on() local
36 if (cfg->de != NULL) { in modbus_serial_tx_on()
37 gpio_pin_set(cfg->de->port, cfg->de->pin, 1); in modbus_serial_tx_on()
40 uart_irq_tx_enable(cfg->dev); in modbus_serial_tx_on()
45 struct modbus_serial_config *cfg = ctx->cfg; in modbus_serial_tx_off() local
47 uart_irq_tx_disable(cfg->dev); in modbus_serial_tx_off()
48 if (cfg->de != NULL) { in modbus_serial_tx_off()
49 gpio_pin_set(cfg->de->port, cfg->de->pin, 0); in modbus_serial_tx_off()
55 struct modbus_serial_config *cfg = ctx->cfg; in modbus_serial_rx_on() local
57 if (cfg->re != NULL) { in modbus_serial_rx_on()
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| /Zephyr-Core-3.7.0/drivers/dma/ |
| D | dma_intel_adsp_hda.c | 34 const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; in intel_adsp_hda_dma_host_in_config() local
39 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_in_config()
43 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_in_config()
49 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_in_config()
53 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_in_config()
56 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_in_config()
68 const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; in intel_adsp_hda_dma_host_out_config() local
73 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_out_config()
77 __ASSERT(dma_cfg->channel_direction == cfg->direction, in intel_adsp_hda_dma_host_out_config()
84 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_out_config()
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| /Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/ |
| D | nxp-s32-pinctrl.h | 36 #define NXP_S32_PINMUX_MSCR_SSS(cfg) \ argument
37 (((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT)
39 #define NXP_S32_PINMUX_IMCR_SSS(cfg) \ argument
40 (((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT)
42 #define NXP_S32_PINMUX_IMCR_IDX(cfg) \ argument
43 (((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT)
45 #define NXP_S32_PINMUX_MSCR_IDX(cfg) \ argument
46 (((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT)
48 #define NXP_S32_PINMUX_MSCR_SIUL2_IDX(cfg) \ argument
49 (((cfg) & NXP_S32_MSCR_SIUL2_IDX_MASK) << NXP_S32_MSCR_SIUL2_IDX_SHIFT)
[all …]
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| /Zephyr-Core-3.7.0/drivers/modem/ |
| D | modem_socket.c | 22 uint16_t modem_socket_next_packet_size(struct modem_socket_config *cfg, struct modem_socket *sock) in modem_socket_next_packet_size() argument
26 k_sem_take(&cfg->sem_lock, K_FOREVER); in modem_socket_next_packet_size()
35 k_sem_give(&cfg->sem_lock); in modem_socket_next_packet_size()
72 int modem_socket_packet_size_update(struct modem_socket_config *cfg, struct modem_socket *sock, in modem_socket_packet_size_update() argument
81 k_sem_take(&cfg->sem_lock, K_FOREVER); in modem_socket_packet_size_update()
92 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
120 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
128 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
138 k_sem_give(&cfg->sem_lock); in modem_socket_packet_size_update()
150 int modem_socket_get(struct modem_socket_config *cfg, int family, int type, int proto) in modem_socket_get() argument
[all …]
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| /Zephyr-Core-3.7.0/drivers/serial/ |
| D | uart_lpc11u6x.c | 19 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_poll_in() local
21 if (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_RDR)) { in lpc11u6x_uart0_poll_in()
24 *c = cfg->uart0->rbr; in lpc11u6x_uart0_poll_in()
31 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_poll_out() local
33 while (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_THRE)) { in lpc11u6x_uart0_poll_out()
35 cfg->uart0->thr = c; in lpc11u6x_uart0_poll_out()
40 const struct lpc11u6x_uart0_config *cfg = dev->config; in lpc11u6x_uart0_err_check() local
44 lsr = cfg->uart0->lsr; in lpc11u6x_uart0_err_check()
78 const struct lpc11u6x_uart0_config *cfg, in lpc11u6x_uart0_config_baudrate() argument
89 clock_control_get_rate(clk_drv, (clock_control_subsys_t) cfg->clkid, in lpc11u6x_uart0_config_baudrate()
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| D | usart_gd32.c | 56 const struct gd32_usart_config *const cfg = dev->config; in usart_gd32_init() local
62 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in usart_gd32_init()
71 switch (cfg->parity) { in usart_gd32_init()
89 (clock_control_subsys_t)&cfg->clkid); in usart_gd32_init()
91 (void)reset_line_toggle_dt(&cfg->reset); in usart_gd32_init()
93 usart_baudrate_set(cfg->reg, data->baud_rate); in usart_gd32_init()
94 usart_parity_config(cfg->reg, parity); in usart_gd32_init()
95 usart_word_length_set(cfg->reg, word_length); in usart_gd32_init()
97 usart_stop_bit_set(cfg->reg, USART_STB_1BIT); in usart_gd32_init()
98 usart_receive_config(cfg->reg, USART_RECEIVE_ENABLE); in usart_gd32_init()
[all …]
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| D | uart_sam.c | 47 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_poll_in() local
49 Uart * const uart = cfg->regs; in uart_sam_poll_in()
63 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_poll_out() local
65 Uart * const uart = cfg->regs; in uart_sam_poll_out()
77 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_err_check() local
79 volatile Uart * const uart = cfg->regs; in uart_sam_err_check()
103 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_baudrate_set() local
105 volatile Uart * const uart = cfg->regs; in uart_sam_baudrate_set()
145 const struct uart_sam_dev_cfg *const cfg = dev->config; in uart_sam_get_parity() local
147 volatile Uart * const uart = cfg->regs; in uart_sam_get_parity()
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| /Zephyr-Core-3.7.0/drivers/clock_control/ |
| D | clock_control_sam_pmc.c | 26 const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys; in atmel_sam_clock_control_on() local
28 if (cfg == NULL) { in atmel_sam_clock_control_on()
33 LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id); in atmel_sam_clock_control_on()
35 switch (cfg->clock_type) { in atmel_sam_clock_control_on()
37 soc_pmc_peripheral_enable(cfg->peripheral_id); in atmel_sam_clock_control_on()
52 const struct atmel_sam_pmc_config *cfg = (const struct atmel_sam_pmc_config *)sys; in atmel_sam_clock_control_off() local
54 if (cfg == NULL) { in atmel_sam_clock_control_off()
59 LOG_DBG("Type: %x, Id: %d", cfg->clock_type, cfg->peripheral_id); in atmel_sam_clock_control_off()
61 switch (cfg->clock_type) { in atmel_sam_clock_control_off()
63 soc_pmc_peripheral_disable(cfg->peripheral_id); in atmel_sam_clock_control_off()
[all …]
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| /Zephyr-Core-3.7.0/drivers/dai/nxp/esai/ |
| D | esai.c | 35 struct esai_transceiver_config *cfg) in esai_get_clock_rate_config() argument
40 if (!cfg) { in esai_get_clock_rate_config()
87 cfg->hclk_bypass = true; in esai_get_clock_rate_config()
97 cfg->hclk_prescaler_en = true; in esai_get_clock_rate_config()
113 cfg->hclk_div_ratio = hclk_div_ratio; in esai_get_clock_rate_config()
122 if (variable_hclk || cfg->hclk_bypass) { in esai_get_clock_rate_config()
131 cfg->hclk_prescaler_en = true; in esai_get_clock_rate_config()
137 cfg->bclk_div_ratio = 1; in esai_get_clock_rate_config()
138 cfg->hclk_div_ratio = hclk_div_ratio; in esai_get_clock_rate_config()
148 cfg->bclk_div_ratio = bclk_div_ratio; in esai_get_clock_rate_config()
[all …]
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| /Zephyr-Core-3.7.0/drivers/input/ |
| D | input_kbd_matrix.c | 28 const struct input_kbd_matrix_common_config *cfg = dev->config; in input_kbd_matrix_ghosting() local
29 const kbd_row_t *state = cfg->matrix_new_state; in input_kbd_matrix_ghosting()
45 for (int c = 0; c < cfg->col_size; c++) { in input_kbd_matrix_ghosting()
50 for (int c_next = c + 1; c_next < cfg->col_size; c_next++) { in input_kbd_matrix_ghosting()
73 const struct input_kbd_matrix_common_config *cfg = dev->config; in input_kbd_matrix_drive_column() local
74 const struct input_kbd_matrix_api *api = cfg->api; in input_kbd_matrix_drive_column()
85 const struct input_kbd_matrix_common_config *cfg = dev->config; in input_kbd_matrix_scan() local
86 const struct input_kbd_matrix_api *api = cfg->api; in input_kbd_matrix_scan()
90 for (int col = 0; col < cfg->col_size; col++) { in input_kbd_matrix_scan()
91 if (cfg->actual_key_mask != NULL && in input_kbd_matrix_scan()
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| /Zephyr-Core-3.7.0/subsys/ipc/ipc_service/lib/ |
| D | pbuf.c | 27 static int validate_cfg(const struct pbuf_cfg *cfg) in validate_cfg() argument
30 if (!cfg || !cfg->rd_idx_loc || !cfg->wr_idx_loc || !cfg->data_loc) { in validate_cfg()
35 if (!IS_PTR_ALIGNED_BYTES(cfg->rd_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) || in validate_cfg()
36 !IS_PTR_ALIGNED_BYTES(cfg->wr_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) || in validate_cfg()
37 !IS_PTR_ALIGNED_BYTES(cfg->data_loc, _PBUF_IDX_SIZE)) { in validate_cfg()
42 if (cfg->len < _PBUF_MIN_DATA_LEN || !IS_PTR_ALIGNED_BYTES(cfg->len, _PBUF_IDX_SIZE)) { in validate_cfg()
47 if (!(cfg->rd_idx_loc < cfg->wr_idx_loc) || in validate_cfg()
48 !((uint8_t *)cfg->wr_idx_loc < cfg->data_loc) || in validate_cfg()
49 !(((uint8_t *)cfg->rd_idx_loc + MAX(_PBUF_IDX_SIZE, cfg->dcache_alignment)) == in validate_cfg()
50 (uint8_t *)cfg->wr_idx_loc)) { in validate_cfg()
[all …]
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| /Zephyr-Core-3.7.0/drivers/pwm/ |
| D | pwm_stm32.c | 316 const struct pwm_stm32_config *cfg = dev->config; in pwm_stm32_set_cycles() local
331 if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer) && in pwm_stm32_set_cycles()
337 if (LL_TIM_IsEnabledIT_CC1(cfg->timer) || LL_TIM_IsEnabledIT_CC2(cfg->timer) || in pwm_stm32_set_cycles()
338 LL_TIM_IsEnabledIT_CC3(cfg->timer) || LL_TIM_IsEnabledIT_CC4(cfg->timer)) { in pwm_stm32_set_cycles()
367 LL_TIM_CC_DisableChannel(cfg->timer, current_ll_channel); in pwm_stm32_set_cycles()
371 if (cfg->countermode == LL_TIM_COUNTERMODE_UP) { in pwm_stm32_set_cycles()
374 } else if (cfg->countermode == LL_TIM_COUNTERMODE_DOWN) { in pwm_stm32_set_cycles()
379 } else if (is_center_aligned(cfg->countermode)) { in pwm_stm32_set_cycles()
386 if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, current_ll_channel)) { in pwm_stm32_set_cycles()
400 oc_init.OCState = LL_TIM_CC_IsEnabledChannel(cfg->timer, ll_channel) in pwm_stm32_set_cycles()
[all …]
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| D | pwm_gecko.c | 31 const struct pwm_gecko_config *cfg = dev->config; in pwm_gecko_set_cycles() local
33 if (BUS_RegMaskedRead(&cfg->timer->CC[channel].CTRL, in pwm_gecko_set_cycles()
37 BUS_RegMaskedWrite(&cfg->timer->ROUTE, in pwm_gecko_set_cycles()
39 cfg->location << _TIMER_ROUTE_LOCATION_SHIFT); in pwm_gecko_set_cycles()
40 BUS_RegMaskedSet(&cfg->timer->ROUTE, 1 << channel); in pwm_gecko_set_cycles()
42 BUS_RegMaskedWrite(&cfg->timer->ROUTELOC0, in pwm_gecko_set_cycles()
45 cfg->location << (channel * _TIMER_ROUTELOC0_CC1LOC_SHIFT)); in pwm_gecko_set_cycles()
46 BUS_RegMaskedSet(&cfg->timer->ROUTEPEN, 1 << channel); in pwm_gecko_set_cycles()
52 TIMER_InitCC(cfg->timer, channel, &compare_config); in pwm_gecko_set_cycles()
55 cfg->timer->CC[channel].CTRL |= (flags & PWM_POLARITY_INVERTED) ? in pwm_gecko_set_cycles()
[all …]
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| /Zephyr-Core-3.7.0/subsys/net/ip/ |
| D | ipv4_autoconf.c | 60 struct net_if_config *cfg; in acd_event_handler() local
63 cfg = net_if_get_config(iface); in acd_event_handler()
64 if (!cfg) { in acd_event_handler()
68 if (cfg->ipv4auto.iface == NULL) { in acd_event_handler()
84 if (!net_ipv4_addr_cmp(&cfg->ipv4auto.requested_ip, addr)) { in acd_event_handler()
90 cfg->ipv4auto.state = NET_IPV4_AUTOCONF_ASSIGNED; in acd_event_handler()
97 cfg->ipv4auto.state = NET_IPV4_AUTOCONF_INIT; in acd_event_handler()
98 ipv4_autoconf_addr_set(&cfg->ipv4auto); in acd_event_handler()
108 struct net_if_config *cfg; in net_ipv4_autoconf_start() local
114 cfg = net_if_get_config(iface); in net_ipv4_autoconf_start()
[all …]
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| /Zephyr-Core-3.7.0/drivers/i2c/ |
| D | i2c_gd32.c | 57 static inline void i2c_gd32_enable_interrupts(const struct i2c_gd32_config *cfg) in i2c_gd32_enable_interrupts() argument
59 I2C_CTL1(cfg->reg) |= I2C_CTL1_ERRIE; in i2c_gd32_enable_interrupts()
60 I2C_CTL1(cfg->reg) |= I2C_CTL1_EVIE; in i2c_gd32_enable_interrupts()
61 I2C_CTL1(cfg->reg) |= I2C_CTL1_BUFIE; in i2c_gd32_enable_interrupts()
64 static inline void i2c_gd32_disable_interrupts(const struct i2c_gd32_config *cfg) in i2c_gd32_disable_interrupts() argument
66 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_ERRIE; in i2c_gd32_disable_interrupts()
67 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_EVIE; in i2c_gd32_disable_interrupts()
68 I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE; in i2c_gd32_disable_interrupts()
72 const struct i2c_gd32_config *cfg) in i2c_gd32_xfer_read() argument
75 *data->current->buf = I2C_DATA(cfg->reg); in i2c_gd32_xfer_read()
[all …]
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| /Zephyr-Core-3.7.0/drivers/spi/ |
| D | spi_mchp_mss.c | 116 static inline uint32_t mss_spi_read(const struct mss_spi_config *cfg, mm_reg_t offset) in mss_spi_read() argument
118 return sys_read32(cfg->base + offset); in mss_spi_read()
121 static inline void mss_spi_write(const struct mss_spi_config *cfg, mm_reg_t offset, uint32_t val) in mss_spi_write() argument
123 sys_write32(val, cfg->base + offset); in mss_spi_write()
126 static inline void mss_spi_hw_tfsz_set(const struct mss_spi_config *cfg, int len) in mss_spi_hw_tfsz_set() argument
130 mss_spi_write(cfg, MSS_SPI_REG_FRAMESUP, (len & MSS_SPI_FRAMESUP_UP_BYTES_MSK)); in mss_spi_hw_tfsz_set()
131 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL); in mss_spi_hw_tfsz_set()
134 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control); in mss_spi_hw_tfsz_set()
137 static inline void mss_spi_enable_controller(const struct mss_spi_config *cfg) in mss_spi_enable_controller() argument
141 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL); in mss_spi_enable_controller()
[all …]
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| /Zephyr-Core-3.7.0/drivers/regulator/ |
| D | regulator_gpio.c | 35 const struct regulator_gpio_config *cfg = dev->config; in regulator_gpio_apply_state() local
37 for (unsigned int gpio_idx = 0; gpio_idx < cfg->num_gpios; gpio_idx++) { in regulator_gpio_apply_state()
41 ret = gpio_pin_get_dt(&cfg->gpios[gpio_idx]); in regulator_gpio_apply_state()
48 ret = gpio_pin_set_dt(&cfg->gpios[gpio_idx], new_state_of_gpio); in regulator_gpio_apply_state()
61 const struct regulator_gpio_config *cfg = dev->config; in regulator_gpio_enable() local
64 if (cfg->enable.port == NULL) { in regulator_gpio_enable()
68 ret = gpio_pin_set_dt(&cfg->enable, 1); in regulator_gpio_enable()
79 const struct regulator_gpio_config *cfg = dev->config; in regulator_gpio_disable() local
81 if (cfg->enable.port == NULL) { in regulator_gpio_disable()
85 return gpio_pin_set_dt(&cfg->enable, 0); in regulator_gpio_disable()
[all …]
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| /Zephyr-Core-3.7.0/drivers/watchdog/ |
| D | wdt_ene_kb1200.c | 29 struct wdt_kb1200_config const *cfg = dev->config; in wdt_kb1200_setup() local
43 cfg->wdt->WDTCFG = WDT_ADCO32K; in wdt_kb1200_setup()
45 cfg->wdt->WDTCFG = WDT_PHER32K; in wdt_kb1200_setup()
48 cfg->wdt->WDTPF = (WDT_HALF_WAY_EVENT | WDT_RESET_EVENT); in wdt_kb1200_setup()
50 cfg->wdt->WDTCFG |= WDT_FUNCTON_ENABLE; in wdt_kb1200_setup()
57 struct wdt_kb1200_config const *cfg = dev->config; in wdt_kb1200_disable() local
60 if (!(cfg->wdt->WDTCFG & WDT_FUNCTON_ENABLE)) { in wdt_kb1200_disable()
64 cfg->wdt->WDTCFG = (cfg->wdt->WDTCFG & ~WDT_FUNCTON_ENABLE) | WDT_DISABLE_PASSWORD; in wdt_kb1200_disable()
66 cfg->wdt->WDTPF = (WDT_HALF_WAY_EVENT | WDT_RESET_EVENT); in wdt_kb1200_disable()
68 cfg->wdt->WDTIE &= ~WDT_HALF_WAY_EVENT; in wdt_kb1200_disable()
[all …]
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| /Zephyr-Core-3.7.0/drivers/sdhc/ |
| D | imx_usdhc.c | 151 const struct usdhc_config *cfg = dev->config; in card_detect_gpio_cb() local
154 if (gpio_pin_get_dt(&cfg->detect_gpio)) { in card_detect_gpio_cb()
171 static int imx_usdhc_dat3_pull(const struct usdhc_config *cfg, bool pullup) in imx_usdhc_dat3_pull() argument
175 ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_NOPULL); in imx_usdhc_dat3_pull()
183 if (cfg->pwr_gpio.port) { in imx_usdhc_dat3_pull()
184 ret = gpio_pin_set_dt(&cfg->pwr_gpio, 0); in imx_usdhc_dat3_pull()
190 ret = gpio_pin_set_dt(&cfg->pwr_gpio, 1); in imx_usdhc_dat3_pull()
207 const struct usdhc_config *cfg = dev->config; in imx_usdhc_error_recovery() local
208 uint32_t status = USDHC_GetPresentStatusFlags(cfg->base); in imx_usdhc_error_recovery()
212 USDHC_Reset(cfg->base, kUSDHC_ResetCommand, 100U); in imx_usdhc_error_recovery()
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| /Zephyr-Core-3.7.0/samples/drivers/audio/dmic/src/ |
| D | main.c | 32 struct dmic_cfg *cfg, in do_pdm_transfer() argument
38 cfg->streams[0].pcm_rate, cfg->channel.req_num_chan); in do_pdm_transfer()
40 ret = dmic_configure(dmic_dev, cfg); in do_pdm_transfer()
92 struct dmic_cfg cfg = { in main() local
109 cfg.channel.req_num_chan = 1; in main()
110 cfg.channel.req_chan_map_lo = in main()
112 cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE; in main()
113 cfg.streams[0].block_size = in main()
114 BLOCK_SIZE(cfg.streams[0].pcm_rate, cfg.channel.req_num_chan); in main()
116 ret = do_pdm_transfer(dmic_dev, &cfg, 2 * BLOCK_COUNT); in main()
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| /Zephyr-Core-3.7.0/tests/drivers/input/kbd_matrix/src/ |
| D | main.c | 151 const struct input_kbd_matrix_common_config *cfg = test_dev->config; in ZTEST() local
156 k_sleep(K_USEC(cfg->debounce_down_us / 2)); in ZTEST()
159 k_sleep(K_USEC(cfg->debounce_down_us)); in ZTEST()
163 k_sleep(K_USEC(cfg->debounce_up_us / 2)); in ZTEST()
166 k_sleep(K_USEC(cfg->debounce_up_us)); in ZTEST()
179 const struct input_kbd_matrix_common_config *cfg = test_dev->config; in ZTEST() local
184 k_sleep(K_USEC(cfg->debounce_down_us / 2)); in ZTEST()
188 k_sleep(K_USEC(cfg->debounce_down_us)); in ZTEST()
198 const struct input_kbd_matrix_common_config *cfg = test_dev->config; in ZTEST() local
203 k_sleep(K_USEC(cfg->debounce_down_us / 2)); in ZTEST()
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| /Zephyr-Core-3.7.0/drivers/sensor/veaa_x_3/ |
| D | veaa_x_3.c | 39 static uint16_t veaa_x_3_kpa_range(const struct veaa_x_3_cfg *cfg) in veaa_x_3_kpa_range() argument
41 return cfg->kpa_max - cfg->kpa_min; in veaa_x_3_kpa_range()
47 const struct veaa_x_3_cfg *cfg = dev->config; in veaa_x_3_attr_set() local
56 if (val->val1 > cfg->kpa_max || val->val1 < cfg->kpa_min) { in veaa_x_3_attr_set()
62 tmp = val->val1 - cfg->kpa_min; in veaa_x_3_attr_set()
63 if (u32_mul_overflow(tmp, BIT(cfg->dac_resolution) - 1, &tmp)) { in veaa_x_3_attr_set()
67 tmp /= veaa_x_3_kpa_range(cfg); in veaa_x_3_attr_set()
69 return dac_write_value(cfg->dac, cfg->dac_channel, tmp); in veaa_x_3_attr_set()
78 const struct veaa_x_3_cfg *cfg = dev->config; in veaa_x_3_attr_get() local
86 val->val1 = cfg->kpa_min; in veaa_x_3_attr_get()
[all …]
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| /Zephyr-Core-3.7.0/drivers/w1/ |
| D | w1_ds2477_85_common.c | 22 const struct w1_ds2477_85_config *cfg = dev->config; in ds2477_85_write_port_config() local
29 ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_WR_W1_PORT_CFG_LEN + CMD_OVERHEAD_LEN)); in ds2477_85_write_port_config()
34 k_usleep(cfg->t_op_us); in ds2477_85_write_port_config()
36 ret = i2c_read_dt(&cfg->i2c_spec, buf, 2); in ds2477_85_write_port_config()
49 const struct w1_ds2477_85_config *cfg = dev->config; in ds2477_85_read_port_config() local
55 ret = i2c_write_dt(&cfg->i2c_spec, buf, (CMD_RD_W1_PORT_CFG_LEN + CMD_OVERHEAD_LEN)); in ds2477_85_read_port_config()
60 k_usleep(cfg->t_op_us); in ds2477_85_read_port_config()
62 ret = i2c_read_dt(&cfg->i2c_spec, buf, 4); in ds2477_85_read_port_config()
77 const struct w1_ds2477_85_config *cfg = dev->config; in ds2477_85_reset_master() local
81 ret = i2c_write_dt(&cfg->i2c_spec, buf, 1); in ds2477_85_reset_master()
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| /Zephyr-Core-3.7.0/drivers/sensor/st/lis2dw12/ |
| D | lis2dw12_trigger.c | 28 const struct lis2dw12_device_config *cfg = dev->config; in lis2dw12_enable_int() local
29 stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; in lis2dw12_enable_int()
34 if (cfg->int_pin == 1) { in lis2dw12_enable_int()
113 const struct lis2dw12_device_config *cfg = dev->config; in lis2dw12_trigger_set() local
114 stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx; in lis2dw12_trigger_set()
119 if (cfg->gpio_int.port == NULL) { in lis2dw12_trigger_set()
138 if ((cfg->tap_threshold[0] == 0) && in lis2dw12_trigger_set()
139 (cfg->tap_threshold[1] == 0) && in lis2dw12_trigger_set()
140 (cfg->tap_threshold[2] == 0)) { in lis2dw12_trigger_set()
251 const struct lis2dw12_device_config *cfg = dev->config; in lis2dw12_handle_interrupt() local
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| /Zephyr-Core-3.7.0/boards/silabs/dev_kits/sltb004a/ |
| D | board.c | 17 static int enable_supply(const struct supply_cfg *cfg) in enable_supply() argument
21 if (device_is_ready(cfg->gpio)) { in enable_supply()
22 gpio_pin_configure(cfg->gpio, cfg->pin, in enable_supply()
23 GPIO_OUTPUT | cfg->flags); in enable_supply()
24 gpio_pin_set(cfg->gpio, cfg->pin, 1); in enable_supply()
33 struct supply_cfg cfg; in efr32mg_sltb004a_init() local
36 (void)cfg; in efr32mg_sltb004a_init()
41 cfg = (struct supply_cfg){ in efr32mg_sltb004a_init()
48 rc = enable_supply(&cfg); in efr32mg_sltb004a_init()
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