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Searched refs:bdiv (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.7.0/drivers/serial/
Duart_cdns.c40 uart_regs->baud_rate_div = dev_cfg->bdiv; in uart_cdns_set_baudrate()
51 uart_regs->baud_rate_gen = (dev_cfg->sys_clk_freq + ((dev_cfg->bdiv + 1) * baud_rate) / 2) / in uart_cdns_set_baudrate()
52 ((dev_cfg->bdiv + 1) * baud_rate); in uart_cdns_set_baudrate()
301 .bdiv = DT_INST_PROP(n, bdiv), \
Duart_cdns.h131 uint32_t bdiv; member
/Zephyr-Core-3.7.0/tests/drivers/build_all/uart/boards/
Dqemu_cortex_m3.overlay15 bdiv = <4>;
/Zephyr-Core-3.7.0/drivers/dai/intel/ssp/
Dssp.c1252 uint32_t bdiv; in dai_ssp_set_config_tplg() local
1459 bdiv = ssp_plat_data->params.bclk_rate / ssp_plat_data->params.fsync_rate; in dai_ssp_set_config_tplg()
1460 if (bdiv < ssp_plat_data->params.tdm_slot_width * ssp_plat_data->params.tdm_slots) { in dai_ssp_set_config_tplg()
1477 if (bdiv < bdiv_min) { in dai_ssp_set_config_tplg()
1478 LOG_ERR("bdiv(%d) < bdiv_min(%d)", bdiv, bdiv_min); in dai_ssp_set_config_tplg()
1483 frame_end_padding = bdiv - bdiv_min; in dai_ssp_set_config_tplg()
1498 if (bdiv % 2) { in dai_ssp_set_config_tplg()
1499 LOG_ERR("bdiv %d is not divisible by 2", bdiv); in dai_ssp_set_config_tplg()
1505 frame_len = bdiv / 2; in dai_ssp_set_config_tplg()
1549 if (bdiv % 2) { in dai_ssp_set_config_tplg()
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