Searched refs:bclk_div_ratio (Results 1 – 2 of 2) sorted by relevance
37 uint32_t hclk_div_ratio, bclk_div_ratio; in esai_get_clock_rate_config() local73 bclk_div_ratio = 1; in esai_get_clock_rate_config()137 cfg->bclk_div_ratio = 1; in esai_get_clock_rate_config()144 bclk_div_ratio = DIV_ROUND_UP(extal_rate / hclk_div_ratio, bclk_rate); in esai_get_clock_rate_config()146 if (bclk_div_ratio <= 16) { in esai_get_clock_rate_config()148 cfg->bclk_div_ratio = bclk_div_ratio; in esai_get_clock_rate_config()162 bclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); in esai_get_clock_rate_config()164 if (bclk_div_ratio > 16) { in esai_get_clock_rate_config()171 cfg->bclk_div_ratio = bclk_div_ratio; in esai_get_clock_rate_config()264 cfg->bclk_div_ratio = 1; in esai_get_xceiver_default_config()[all …]
217 uint32_t bclk_div_ratio; member488 LOG_DBG("BCLK divider ratio: %d", cfg->bclk_div_ratio); in esai_dump_xceiver_config()
