| /Zephyr-Core-3.7.0/drivers/flash/ |
| D | flash_cadence_nand_ll.c | 16 static inline int32_t cdns_nand_wait_idle(uintptr_t base_address) in cdns_nand_wait_idle() argument
19 if (!WAIT_FOR(CNF_GET_CTRL_BUSY(sys_read32(CNF_CMDREG(base_address, CTRL_STATUS))) == 0U, in cdns_nand_wait_idle()
58 uintptr_t base_address; in cdns_nand_device_info() local
62 base_address = params->nand_base; in cdns_nand_device_info()
65 reg_value = sys_read32(CNF_CTRLPARAM(base_address, VERSION)); in cdns_nand_device_info()
74 reg_value = sys_read32(CNF_CTRLPARAM(base_address, DEV_PARAMS0)); in cdns_nand_device_info()
85 reg_value = sys_read32(CNF_CTRLCFG(base_address, DEV_LAYOUT)); in cdns_nand_device_info()
89 reg_value = sys_read32(CNF_CTRLPARAM(base_address, DEV_AREA)); in cdns_nand_device_info()
94 params->nblocks_per_lun = sys_read32(CNF_CTRLPARAM(base_address, DEV_BLOCKS_PLUN)); in cdns_nand_device_info()
116 static uint32_t cdns_nand_get_thrd_status(uintptr_t base_address, uint8_t thread) in cdns_nand_get_thrd_status() argument
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| /Zephyr-Core-3.7.0/drivers/syscon/ |
| D | syscon.c | 44 uintptr_t base_address; in syscon_generic_read_reg() local
61 base_address = DEVICE_MMIO_GET(dev); in syscon_generic_read_reg()
65 *val = sys_read8(base_address + reg); in syscon_generic_read_reg()
68 *val = sys_read16(base_address + reg); in syscon_generic_read_reg()
71 *val = sys_read32(base_address + reg); in syscon_generic_read_reg()
84 uintptr_t base_address; in syscon_generic_write_reg() local
97 base_address = DEVICE_MMIO_GET(dev); in syscon_generic_write_reg()
101 sys_write8(val, (base_address + reg)); in syscon_generic_write_reg()
104 sys_write16(val, (base_address + reg)); in syscon_generic_write_reg()
107 sys_write32(val, (base_address + reg)); in syscon_generic_write_reg()
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| /Zephyr-Core-3.7.0/drivers/reset/ |
| D | reset_rpi_pico.c | 19 uintptr_t base_address; member
25 uint32_t base_address = config->base_address; in reset_rpi_read_register() local
29 *value = sys_read8(base_address + offset); in reset_rpi_read_register()
32 *value = sys_read16(base_address + offset); in reset_rpi_read_register()
35 *value = sys_read32(base_address + offset); in reset_rpi_read_register()
47 uint32_t base_address = config->base_address; in reset_rpi_write_register() local
51 sys_write8(value, base_address + offset); in reset_rpi_write_register()
54 sys_write16(value, base_address + offset); in reset_rpi_write_register()
57 sys_write32(value, base_address + offset); in reset_rpi_write_register()
153 .base_address = DT_INST_REG_ADDR(idx), \
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| D | reset_intel_socfpga.c | 29 uintptr_t base_address = DEVICE_MMIO_GET(dev); in reset_intel_soc_status() local
36 value = sys_read32(base_address + offset); in reset_intel_soc_status()
44 uintptr_t base_address = DEVICE_MMIO_GET(dev); in reset_intel_soc_update() local
52 if (sys_test_bit(base_address + offset, regbit) == 0) { in reset_intel_soc_update()
53 sys_set_bit(base_address + offset, regbit); in reset_intel_soc_update()
56 if (sys_test_bit(base_address + offset, regbit) != 0) { in reset_intel_soc_update()
57 sys_clear_bit(base_address + offset, regbit); in reset_intel_soc_update()
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| /Zephyr-Core-3.7.0/drivers/clock_control/ |
| D | clock_control_rv32m1_pcc.c | 18 uint32_t base_address; member
22 (((struct rv32m1_pcc_config *)(dev->config))->base_address)
62 .base_address = DT_INST_REG_ADDR(inst) \
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| D | clock_control_renesas_cpg_mssr.c | 19 static void rcar_cpg_reset(uint32_t base_address, uint32_t reg, uint32_t bit) in rcar_cpg_reset() argument
21 rcar_cpg_write(base_address, srcr[reg], BIT(bit)); in rcar_cpg_reset()
22 rcar_cpg_write(base_address, SRSTCLR(reg), BIT(bit)); in rcar_cpg_reset()
25 void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val) in rcar_cpg_write() argument
27 sys_write32(~val, base_address + CPGWPR); in rcar_cpg_write()
28 sys_write32(val, base_address + reg); in rcar_cpg_write()
33 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable) in rcar_cpg_mstp_clock_endisable() argument
43 reg_val = sys_read32(base_address + mstpcr[reg]); in rcar_cpg_mstp_clock_endisable()
50 sys_write32(reg_val, base_address + mstpcr[reg]); in rcar_cpg_mstp_clock_endisable()
52 rcar_cpg_reset(base_address, reg, bit); in rcar_cpg_mstp_clock_endisable()
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| D | clock_control_mcux_pcc.c | 22 uint32_t base_address; member
27 #define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address)
140 .base_address = DT_INST_REG_ADDR(inst), \
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| D | clock_control_renesas_cpg_mssr.h | 128 void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);
130 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable);
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| /Zephyr-Core-3.7.0/drivers/audio/ |
| D | dmic_mcux.c | 36 DMIC_Type *base_address; member
101 DMIC_EnableChannnel(drv_data->base_address, mask); in dmic_mcux_activate_channels()
104 drv_data->base_address->CHANEN &= ~mask; in dmic_mcux_activate_channels()
131 DMIC_EnableChannelDma(drv_data->base_address, in dmic_mcux_enable_dma()
157 src = DMIC_FifoGetAddress(drv_data->base_address, hw_chan); in dmic_mcux_reload_dma()
309 DMIC_FifoGetAddress(drv_data->base_address, hw_chan); in dmic_mcux_setup_dma()
371 DMIC_ConfigChannel(drv_data->base_address, (dmic_channel_t)chan, in dmic_mcux_init_channel()
377 DMIC_FifoChannel(drv_data->base_address, chan, 15, true, true); in dmic_mcux_init_channel()
379 DMIC_EnableChannelInterrupt(drv_data->base_address, chan, false); in dmic_mcux_init_channel()
393 DMIC_Init(drv_data->base_address); in mcux_dmic_init()
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| /Zephyr-Core-3.7.0/drivers/interrupt_controller/ |
| D | intc_intel_vtd.c | 39 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_write_reg32() local
41 sys_write32(value, (base_address + reg)); in vtd_write_reg32()
46 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_read_reg32() local
48 return sys_read32(base_address + reg); in vtd_read_reg32()
54 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_write_reg64() local
56 sys_write64(value, (base_address + reg)); in vtd_write_reg64()
61 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_read_reg64() local
63 return sys_read64(base_address + reg); in vtd_read_reg64()
69 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_send_cmd() local
77 while (!sys_test_bit((base_address + VTD_GSTS_REG), in vtd_send_cmd()
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| /Zephyr-Core-3.7.0/drivers/counter/ |
| D | counter_mchp_xec.c | 37 uint32_t base_address; member
52 _dev->config)->base_address)
329 .base_address = DT_INST_REG_ADDR(inst), \
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| /Zephyr-Core-3.7.0/arch/arm/core/mmu/ |
| D | arm_mmu_priv.h | 102 uint32_t base_address : 12; /* [31] */ member
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| D | arm_mmu.c | 433 l1_page_table.entries[l1_index].l1_section_1m.base_address = in arm_mmu_l1_map_section()
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