1 /* 2 * Copyright (c) 2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 /* 7 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 8 * 9 * Functions here are designed to produce efficient code to 10 * search an Xtensa bitmask of interrupts, inspecting only those bits 11 * declared to be associated with a given interrupt level. Each 12 * dispatcher will handle exactly one flagged interrupt, in numerical 13 * order (low bits first) and will return a mask of that bit that can 14 * then be cleared by the calling code. Unrecognized bits for the 15 * level will invoke an error handler. 16 */ 17 18 #include <xtensa/config/core-isa.h> 19 #include <zephyr/sys/util.h> 20 #include <zephyr/sw_isr_table.h> 21 22 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5 23 #error core-isa.h interrupt level does not match dispatcher! 24 #endif 25 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2 26 #error core-isa.h interrupt level does not match dispatcher! 27 #endif 28 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 29 #error core-isa.h interrupt level does not match dispatcher! 30 #endif 31 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2 32 #error core-isa.h interrupt level does not match dispatcher! 33 #endif 34 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2 35 #error core-isa.h interrupt level does not match dispatcher! 36 #endif 37 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2 38 #error core-isa.h interrupt level does not match dispatcher! 39 #endif 40 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 41 #error core-isa.h interrupt level does not match dispatcher! 42 #endif 43 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 44 #error core-isa.h interrupt level does not match dispatcher! 45 #endif 46 #if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 47 #error core-isa.h interrupt level does not match dispatcher! 48 #endif 49 #if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2 50 #error core-isa.h interrupt level does not match dispatcher! 51 #endif 52 #if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2 53 #error core-isa.h interrupt level does not match dispatcher! 54 #endif 55 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3 56 #error core-isa.h interrupt level does not match dispatcher! 57 #endif 58 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3 59 #error core-isa.h interrupt level does not match dispatcher! 60 #endif 61 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 3 62 #error core-isa.h interrupt level does not match dispatcher! 63 #endif 64 #if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3 65 #error core-isa.h interrupt level does not match dispatcher! 66 #endif 67 #if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3 68 #error core-isa.h interrupt level does not match dispatcher! 69 #endif 70 #if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3 71 #error core-isa.h interrupt level does not match dispatcher! 72 #endif 73 #if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 74 #error core-isa.h interrupt level does not match dispatcher! 75 #endif 76 #if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3 77 #error core-isa.h interrupt level does not match dispatcher! 78 #endif 79 #if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 80 #error core-isa.h interrupt level does not match dispatcher! 81 #endif 82 #if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3 83 #error core-isa.h interrupt level does not match dispatcher! 84 #endif 85 #if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3 86 #error core-isa.h interrupt level does not match dispatcher! 87 #endif 88 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 89 #error core-isa.h interrupt level does not match dispatcher! 90 #endif 91 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 92 #error core-isa.h interrupt level does not match dispatcher! 93 #endif 94 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 95 #error core-isa.h interrupt level does not match dispatcher! 96 #endif 97 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 98 #error core-isa.h interrupt level does not match dispatcher! 99 #endif 100 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 101 #error core-isa.h interrupt level does not match dispatcher! 102 #endif 103 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1 104 #error core-isa.h interrupt level does not match dispatcher! 105 #endif 106 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 107 #error core-isa.h interrupt level does not match dispatcher! 108 #endif 109 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 110 #error core-isa.h interrupt level does not match dispatcher! 111 #endif 112 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1 113 #error core-isa.h interrupt level does not match dispatcher! 114 #endif 115 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1 116 #error core-isa.h interrupt level does not match dispatcher! 117 #endif 118 _xtensa_handle_one_int5(unsigned int mask)119static inline int _xtensa_handle_one_int5(unsigned int mask) 120 { 121 int irq; 122 123 if (mask & BIT(0)) { 124 mask = BIT(0); 125 irq = 0; 126 goto handle_irq; 127 } 128 return 0; 129 handle_irq: 130 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 131 return mask; 132 } 133 _xtensa_handle_one_int2(unsigned int mask)134static inline int _xtensa_handle_one_int2(unsigned int mask) 135 { 136 int irq; 137 138 if (mask & 0x70006) { 139 if (mask & 0x6) { 140 if (mask & BIT(1)) { 141 mask = BIT(1); 142 irq = 1; 143 goto handle_irq; 144 } 145 if (mask & BIT(2)) { 146 mask = BIT(2); 147 irq = 2; 148 goto handle_irq; 149 } 150 } else { 151 if (mask & BIT(16)) { 152 mask = BIT(16); 153 irq = 16; 154 goto handle_irq; 155 } 156 if (mask & BIT(17)) { 157 mask = BIT(17); 158 irq = 17; 159 goto handle_irq; 160 } 161 if (mask & BIT(18)) { 162 mask = BIT(18); 163 irq = 18; 164 goto handle_irq; 165 } 166 } 167 } else { 168 if (mask & 0x180000) { 169 if (mask & BIT(19)) { 170 mask = BIT(19); 171 irq = 19; 172 goto handle_irq; 173 } 174 if (mask & BIT(20)) { 175 mask = BIT(20); 176 irq = 20; 177 goto handle_irq; 178 } 179 } else { 180 if (mask & BIT(21)) { 181 mask = BIT(21); 182 irq = 21; 183 goto handle_irq; 184 } 185 if (mask & BIT(22)) { 186 mask = BIT(22); 187 irq = 22; 188 goto handle_irq; 189 } 190 if (mask & BIT(23)) { 191 mask = BIT(23); 192 irq = 23; 193 goto handle_irq; 194 } 195 } 196 } 197 return 0; 198 handle_irq: 199 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 200 return mask; 201 } 202 _xtensa_handle_one_int3(unsigned int mask)203static inline int _xtensa_handle_one_int3(unsigned int mask) 204 { 205 int irq; 206 207 if (mask & 0x3000038) { 208 if (mask & 0x18) { 209 if (mask & BIT(3)) { 210 mask = BIT(3); 211 irq = 3; 212 goto handle_irq; 213 } 214 if (mask & BIT(4)) { 215 mask = BIT(4); 216 irq = 4; 217 goto handle_irq; 218 } 219 } else { 220 if (mask & BIT(5)) { 221 mask = BIT(5); 222 irq = 5; 223 goto handle_irq; 224 } 225 if (mask & BIT(24)) { 226 mask = BIT(24); 227 irq = 24; 228 goto handle_irq; 229 } 230 if (mask & BIT(25)) { 231 mask = BIT(25); 232 irq = 25; 233 goto handle_irq; 234 } 235 } 236 } else { 237 if (mask & 0x1c000000) { 238 if (mask & BIT(26)) { 239 mask = BIT(26); 240 irq = 26; 241 goto handle_irq; 242 } 243 if (mask & BIT(27)) { 244 mask = BIT(27); 245 irq = 27; 246 goto handle_irq; 247 } 248 if (mask & BIT(28)) { 249 mask = BIT(28); 250 irq = 28; 251 goto handle_irq; 252 } 253 } else { 254 if (mask & BIT(29)) { 255 mask = BIT(29); 256 irq = 29; 257 goto handle_irq; 258 } 259 if (mask & BIT(30)) { 260 mask = BIT(30); 261 irq = 30; 262 goto handle_irq; 263 } 264 if (mask & BIT(31)) { 265 mask = BIT(31); 266 irq = 31; 267 goto handle_irq; 268 } 269 } 270 } 271 return 0; 272 handle_irq: 273 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 274 return mask; 275 } 276 _xtensa_handle_one_int1(unsigned int mask)277static inline int _xtensa_handle_one_int1(unsigned int mask) 278 { 279 int irq; 280 281 if (mask & 0x7c0) { 282 if (mask & 0xc0) { 283 if (mask & BIT(6)) { 284 mask = BIT(6); 285 irq = 6; 286 goto handle_irq; 287 } 288 if (mask & BIT(7)) { 289 mask = BIT(7); 290 irq = 7; 291 goto handle_irq; 292 } 293 } else { 294 if (mask & BIT(8)) { 295 mask = BIT(8); 296 irq = 8; 297 goto handle_irq; 298 } 299 if (mask & BIT(9)) { 300 mask = BIT(9); 301 irq = 9; 302 goto handle_irq; 303 } 304 if (mask & BIT(10)) { 305 mask = BIT(10); 306 irq = 10; 307 goto handle_irq; 308 } 309 } 310 } else { 311 if (mask & 0x1800) { 312 if (mask & BIT(11)) { 313 mask = BIT(11); 314 irq = 11; 315 goto handle_irq; 316 } 317 if (mask & BIT(12)) { 318 mask = BIT(12); 319 irq = 12; 320 goto handle_irq; 321 } 322 } else { 323 if (mask & BIT(13)) { 324 mask = BIT(13); 325 irq = 13; 326 goto handle_irq; 327 } 328 if (mask & BIT(14)) { 329 mask = BIT(14); 330 irq = 14; 331 goto handle_irq; 332 } 333 if (mask & BIT(15)) { 334 mask = BIT(15); 335 irq = 15; 336 goto handle_irq; 337 } 338 } 339 } 340 return 0; 341 handle_irq: 342 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 343 return mask; 344 } 345 _xtensa_handle_one_int0(unsigned int mask)346static inline int _xtensa_handle_one_int0(unsigned int mask) 347 { 348 return 0; 349 } _xtensa_handle_one_int4(unsigned int mask)350static inline int _xtensa_handle_one_int4(unsigned int mask) 351 { 352 return 0; 353 } _xtensa_handle_one_int6(unsigned int mask)354static inline int _xtensa_handle_one_int6(unsigned int mask) 355 { 356 return 0; 357 } _xtensa_handle_one_int7(unsigned int mask)358static inline int _xtensa_handle_one_int7(unsigned int mask) 359 { 360 return 0; 361 } _xtensa_handle_one_int8(unsigned int mask)362static inline int _xtensa_handle_one_int8(unsigned int mask) 363 { 364 return 0; 365 } _xtensa_handle_one_int9(unsigned int mask)366static inline int _xtensa_handle_one_int9(unsigned int mask) 367 { 368 return 0; 369 } _xtensa_handle_one_int10(unsigned int mask)370static inline int _xtensa_handle_one_int10(unsigned int mask) 371 { 372 return 0; 373 } _xtensa_handle_one_int11(unsigned int mask)374static inline int _xtensa_handle_one_int11(unsigned int mask) 375 { 376 return 0; 377 } _xtensa_handle_one_int12(unsigned int mask)378static inline int _xtensa_handle_one_int12(unsigned int mask) 379 { 380 return 0; 381 } _xtensa_handle_one_int13(unsigned int mask)382static inline int _xtensa_handle_one_int13(unsigned int mask) 383 { 384 return 0; 385 } _xtensa_handle_one_int14(unsigned int mask)386static inline int _xtensa_handle_one_int14(unsigned int mask) 387 { 388 return 0; 389 } _xtensa_handle_one_int15(unsigned int mask)390static inline int _xtensa_handle_one_int15(unsigned int mask) 391 { 392 return 0; 393 } 394
