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/Zephyr-Core-3.7.0/soc/openisa/rv32m1/
DKconfig.soc8 this option to target the RI5CY or ZERO-RISCY core. This
21 OpenISA RV32M1 ZERO-RISCY core
Dlinker.ld65 * Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has
/Zephyr-Core-3.7.0/tests/unit/util/
Dmain.c140 #undef ZERO
143 #define ZERO 0 macro
149 zassert_equal(UTIL_OR(SEVEN, ZERO), 7); in ZTEST()
151 zassert_equal(UTIL_OR(ZERO, SEVEN), 7); in ZTEST()
153 zassert_equal(UTIL_OR(ZERO, ZERO), 0); in ZTEST()
157 zassert_equal(UTIL_AND(ZERO, A_BUILD_ERROR), 0); in ZTEST()
159 zassert_equal(UTIL_AND(SEVEN, ZERO), 0); in ZTEST()
161 zassert_equal(UTIL_AND(ZERO, SEVEN), 0); in ZTEST()
163 zassert_equal(UTIL_AND(ZERO, ZERO), 0); in ZTEST()
/Zephyr-Core-3.7.0/boards/openisa/rv32m1_vega/doc/
Dindex.rst22 The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are
24 `RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more
25 flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
26 "secondary" core. The main ZERO-RISCY use-case is as a wireless
42 - 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core)
99 Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently
318 ZERO-RISCY.
326 The RI5CY and ZERO-RISCY cores are configured to use the slow internal
336 connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by
470 One-Time Board Setup For Booting RI5CY or ZERO-RISCY
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/Zephyr-Core-3.7.0/scripts/coredump/gdbstubs/arch/
Drisc_v.py17 ZERO = 0 variable in RegNum