Searched refs:WINDOWBASE (Results 1 – 6 of 6) sorted by relevance
| /Zephyr-Core-3.7.0/scripts/coredump/gdbstubs/arch/ |
| D | xtensa.py | 194 if r == self.gdb_reg_def.RegNum.WINDOWBASE:
301 WINDOWBASE = 34 variable in GdbRegDef_Sample_Controller.RegNum
337 WINDOWBASE = 69 variable in GdbRegDef_ESP32.RegNum
366 WINDOWBASE = 66 variable in GdbRegDef_ESP32S2.RegNum
399 WINDOWBASE = 69 variable in GdbRegDef_ESP32S3.RegNum
440 WINDOWBASE = 70 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
480 WINDOWBASE = 584 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
515 WINDOWBASE = 38 variable in GdbRegDef_DC233C.RegNum
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| /Zephyr-Core-3.7.0/arch/xtensa/core/ |
| D | README_WINDOWS.rst | 16 WINDOWBASE. The register file is cyclic, so for example if NREGS==64
17 and WINDOWBASE is 15, quads 15, 0, 1, and 2 will be visible as
21 window by a immediate number of quads that are added to WINDOWBASE.
34 to WINDOWBASE, at the same time copying the old (now hidden) stack
40 from WINDOWBASE before returning. This is why the CALLINC bits went
52 or 16 bits wide). The bit in windowstart corresponding to WINDOWBASE
61 being brought into A0-A3 (i.e. the new WINDOWBASE) has a set bit
67 register's quad and WINDOWBASE. If there is, the CPU traps to a spill
69 registers, but it's possible to hit registers 12 out from WINDOWBASE,
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| D | gdbstub.c | 30 WINDOWBASE = 72, enumerator
181 case WINDOWBASE: in read_sreg()
182 val = get_one_sreg(WINDOWBASE); in read_sreg()
959 case (XTREG_GRP_SPECIAL + WINDOWBASE): in arch_gdb_init()
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| D | window_vectors.S | 100 rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
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| D | xtensa_asm2_util.S | 48 rsr a3, WINDOWBASE
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| /Zephyr-Core-3.7.0/arch/xtensa/core/startup/ |
| D | reset_vector.S | 554 wsr a0, WINDOWBASE
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