| /Zephyr-Core-3.7.0/include/zephyr/dt-bindings/clock/ |
| D | stm32c0_clock.h | 68 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32f0_clock.h | 69 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) macro
|
| D | stm32l0_clock.h | 70 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32wb_clock.h | 80 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32wl_clock.h | 77 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32f3_clock.h | 73 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) macro
|
| D | stm32wba_clock.h | 80 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) macro
|
| D | stm32g0_clock.h | 75 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32f7_clock.h | 87 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, DCKCFGR2_REG) macro
|
| D | stm32g4_clock.h | 79 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32l4_clock.h | 77 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) macro
|
| D | stm32h7rs_clock.h | 116 #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG) macro
|
| D | stm32u5_clock.h | 88 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) macro
|
| D | stm32h5_clock.h | 89 #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR1_REG) macro
|
| /Zephyr-Core-3.7.0/samples/boards/stm32/power_mgmt/serial_wakeup/boards/ |
| D | stm32l562e_dk.overlay | 44 <&rcc STM32_SRC_HSI USART1_SEL(2)>;
|
| D | b_u585i_iot02a.overlay | 18 <&rcc STM32_SRC_HSI16 USART1_SEL(2)>;
|
| D | nucleo_wb55rg.overlay | 19 <&rcc STM32_SRC_HSI USART1_SEL(2)>;
|
| /Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | clear_clocks.overlay | 20 <&rcc STM32_SRC_CSI USART1_SEL(4)>;
|
| /Zephyr-Core-3.7.0/boards/st/nucleo_wba55cg/ |
| D | nucleo_wba55cg.dts | 117 <&rcc STM32_SRC_HSI16 USART1_SEL(2)>;
|
