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Searched refs:STM32_PLL3_Q_DIVISOR (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_stm32_ll_h5.c325 STM32_PLL3_Q_DIVISOR); in stm32_clock_control_get_subsys_rate()
584 LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR); in set_up_plls()
Dclock_stm32_ll_u5.c339 STM32_PLL3_Q_DIVISOR); in stm32_clock_control_get_subsys_rate()
670 LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c626 STM32_PLL3_Q_DIVISOR);
905 LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
/Zephyr-Core-3.7.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h210 #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1) macro