1 /*
2  * Copyright (c) 2022 Intel Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef __INTEL_DAI_DRIVER_SSP_REGSV3_H__
8 #define __INTEL_DAI_DRIVER_SSP_REGSV3_H__
9 
10 /* SSP register offsets */
11 #define SSCR0			0x00
12 #define SSCR1			0x04
13 #define SSSR			0x08
14 #define SSITR			0x0C
15 #define SSTO			0x28
16 #define SSPSP			0x2C
17 #define SSTSS			0x38
18 #define SSCR2			0x40
19 #define SSPSP2			0x44
20 
21 #define SSIOC			0x4C
22 #define SSGFS			0x50
23 
24 #define I2SIPCMC		8
25 #define SSMIDyCS(y)		0x60 + 0x10*y
26 #define SSMIDyD(y)		0x64 + 0x10*y
27 #define SSMIDyTSA(y)	0x68 + 0x10*y
28 #define SSMODyCS(y)		0x60 + 0x10*I2SIPCMC + 0x10*y
29 #define SSMODyD(y)		0x64 + 0x10*I2SIPCMC + 0x10*y
30 #define SSMODyTSA(y)	0x68 + 0x10*I2SIPCMC + 0x10*y
31 
32 #define PCMSyCM_OFFSET(x)	0x16 + 0x4*(x)
33 
34 #define OUT_FIFO		SSMODyD(0)
35 #define IN_FIFO			SSMIDyD(0)
36 
37 /* SSCR0 bits */
38 #define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
39 #define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
40 #define SSCR0_FRF		DAI_INTEL_SSP_MASK(5, 4)
41 #define SSCR0_MOT		DAI_INTEL_SSP_SET_BITS(5, 4, 0)
42 #define SSCR0_TI		DAI_INTEL_SSP_SET_BITS(5, 4, 1)
43 #define SSCR0_NAT		DAI_INTEL_SSP_SET_BITS(5, 4, 2)
44 #define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
45 #define SSCR0_RSVD1		BIT(6)
46 #define SSCR0_SSE		BIT(7)
47 #define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
48 #define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
49 #define SSCR0_EDSS		BIT(20)
50 #define SSCR0_RSVD2		BIT(21)
51 #define SSCR0_RIM		BIT(22)
52 #define SSCR0_TIM		BIT(23)
53 #define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
54 #define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
55 #define SSCR0_EFRDC     BIT(27)
56 #define SSCR0_EFRDC2    BIT(28)
57 #define SSCR0_DLE		DAI_INTEL_SSP_SET_BITS(30, 29, 0)
58 #define SSCR0_ACS		BIT(30)
59 #define SSCR0_MOD		BIT(31)
60 
61 /* SSCR1 bits */
62 #define SSCR1_RIE		BIT(0)
63 #define SSCR1_TIE		BIT(1)
64 #define SSCR1_LBM		BIT(2)
65 #define SSCR1_RSVD1		DAI_INTEL_SSP_MASK(15, 3)
66 #define SSCR1_IFS		BIT(16)
67 #define SSCR1_PINTE		BIT(18)
68 #define SSCR1_TINTE		BIT(19)
69 #define SSCR1_RSVD21		DAI_INTEL_SSP_MASK(21, 20)
70 #define SSCR1_TRAIL		BIT(22)
71 #define SSCR1_RWOT		BIT(23)
72 #define SSCR1_SFRMDIR		BIT(24)
73 #define SSCR1_SCLKDIR		BIT(25)
74 #define SSCR1_SCFR		BIT(28)
75 #define SSCR1_EBCEI		BIT(29)
76 #define SSCR1_TTE		BIT(30)
77 #define SSCR1_TTELP		BIT(31)
78 
79 #define SSCR2_TURM1		BIT(1)
80 #define SSCR2_PSPSRWFDFD	BIT(3)
81 #define SSCR2_PSPSTWFDFD	BIT(4)
82 #define SSCR2_SDFD		BIT(14)
83 #define SSCR2_SDPM		BIT(16)
84 #define SSCR2_LJDFD		BIT(17)
85 #define SSCR2_MMRATF		BIT(18)
86 #define SSCR2_SMTATF		BIT(19)
87 #define SSCR2_SFRMEN		BIT(20)
88 #define SSCR2_ACIOLBS		BIT(21)
89 
90 /* SSR bits */
91 #define SSSR_BSY		BIT(4)
92 #define SSSR_ROR		BIT(7)
93 #define SSSR_TUR		BIT(21)
94 
95 /* SSPSP bits */
96 #define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)
97 #define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)
98 #define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)
99 #define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
100 #define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)
101 #define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)
102 #define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)
103 #define SSPSP_DMYSTOP_BITS	2
104 #define SSPSP_DMYSTOP_MASK	DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
105 #define SSPSP_FSRT		BIT(25)
106 #define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)
107 
108 #define SSPSP2			0x44
109 #define SSPSP2_FEP_MASK		0xff
110 
111 #define SSPSP2_RFAC		DAI_INTEL_SSP_MASK(9, 8)
112 #define SSPSP2_TFAC		DAI_INTEL_SSP_MASK(11, 10)
113 #define SSPSP2_EFEP		DAI_INTEL_SSP_MASK(13, 12)
114 #define SSPSP2_ESFRMDW	DAI_INTEL_SSP_MASK(15, 14)
115 
116 
117 #define SSCR3			0x48
118 #define SSIOC			0x4C
119 #define SSP_REG_MAX		SSIOC
120 
121 /* SSTSA bits */
122 #define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
123 #define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
124 
125 /* SSRSA bits */
126 #define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
127 #define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
128 
129 /* SSCR3 bits */
130 #define SSCR3_FRM_MST_EN	BIT(0)
131 #define SSCR3_I2S_MODE_EN	BIT(1)
132 #define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)
133 #define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
134 #define SSCR3_I2S_RX_SS_FIX_EN	BIT(4)
135 #define SSCR3_I2S_TX_EN		BIT(9)
136 #define SSCR3_I2S_RX_EN		BIT(10)
137 #define SSCR3_CLK_EDGE_SEL	BIT(12)
138 #define SSCR3_STRETCH_TX	BIT(14)
139 #define SSCR3_STRETCH_RX	BIT(15)
140 #define SSCR3_MST_CLK_EN	BIT(16)
141 #define SSCR3_SYN_FIX_EN	BIT(17)
142 
143 /* SSCR4 bits */
144 #define SSCR4_TOT_FRM_PRD(x)	((x) << 7)
145 
146 /* SSCR5 bits */
147 #define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)
148 #define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)
149 
150 /* SFIFOTT bits */
151 #define SFIFOTT_TX(x)		((x) - 1)
152 #define SFIFOTT_RX(x)		(((x) - 1) << 16)
153 
154 /* SFIFOL bits */
155 #define SFIFOL_TFL(x)		((x) & 0xFFFF)
156 #define SFIFOL_RFL(x)		((x) >> 16)
157 
158 #define SSTSA_TSEN			BIT(8)
159 #define SSRSA_RSEN			BIT(8)
160 
161 #define SSCR3_TFL_MASK	DAI_INTEL_SSP_MASK(5, 0)
162 #define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
163 #define SSCR3_TFL_VAL(scr3_val)	(((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
164 #define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
165 #define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
166 #define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
167 
168 #define SSIOC_TXDPDEB	BIT(1)
169 #define SSIOC_SFCR		BIT(4)
170 #define SSIOC_SCOE		BIT(5)
171 
172 /* SSMIDyCS */
173 #define SSMIDyCS_RXEN			BIT(0)
174 #define SSMIDyCS_RSRE			BIT(1)
175 #define SSMIDyCS_RFL			DAI_INTEL_SSP_MASK(23, 16)
176 #define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
177 #define SSMIDyCS_RNE			BIT(26)
178 #define SSMIDyCS_RFS			BIT(27)
179 #define SSMIDyCS_ROR			BIT(28)
180 #define SSMIDyCS_PINT			BIT(29)
181 #define SSMIDyCS_TINT			BIT(30)
182 #define SSMIDyCS_EOC			BIT(31)
183 
184 /* SSMIDyTSA */
185 #define SSMIDyTSA_RTSA			DAI_INTEL_SSP_MASK(63, 0)
186 #define SSMIDyTSA_SRTSA(x)		DAI_INTEL_SSP_MASK(63, 0, x)
187 
188 /* SSMODyCS */
189 #define SSMODyCS_TXEN			BIT(0)
190 #define SSMODyCS_TSRE			BIT(1)
191 #define SSMODyCS_TFL			DAI_INTEL_SSP_MASK(23, 16)
192 #define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
193 #define SSMODyCS_TNF			BIT(26)
194 #define SSMODyCS_TFS			BIT(27)
195 #define SSMODyCS_TUR			BIT(28)
196 
197 /* SSMODyTSA */
198 #define SSMODyTSA_TTSA		DAI_INTEL_SSP_MASK(63, 0)
199 #define SSMODyTSA_STTSA(x)	DAI_INTEL_SSP_MASK(63, 0, x)
200 
201 /* For 8000 Hz rate one sample is transmitted within 125us */
202 #define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
203 
204 /* SSP flush retry counts maximum */
205 #define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX	16
206 
207 #define SSP_CLK_MCLK_ES_REQ	BIT(0)
208 #define SSP_CLK_MCLK_ACTIVE	BIT(1)
209 #define SSP_CLK_BCLK_ES_REQ	BIT(2)
210 #define SSP_CLK_BCLK_ACTIVE	BIT(3)
211 
212 #define I2SLCTL_OFFSET		0x04
213 
214 #define I2SLCTL_OFLEN		BIT(4)
215 #define I2SLCTL_SPA(x)		BIT(16 + x)
216 #define I2SLCTL_CPA(x)		BIT(23 + x)
217 
218 #define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
219 #define SHIM_CLKCTL		0x78
220 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
221 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
222 
223 /** \brief Offset of MCLK Divider Control Register. */
224 #define MN_MDIVCTRL 0x100
225 
226 /** \brief Offset of MCLK Divider x Ratio Register. */
227 #define MN_MDIVR(x) (0x180 + (x) * 0x4)
228 
229 /** \brief Enables the output of MCLK Divider. */
230 #define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
231 
232 /** \brief Bits for setting MCLK source clock. */
233 #define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)
234 
235 /** \brief Offset of BCLK x M/N Divider M Value Register. */
236 #define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
237 
238 /** \brief Offset of BCLK x M/N Divider N Value Register. */
239 #define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
240 
241 /** \brief Bits for setting M/N source clock. */
242 #define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)
243 
244 /** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
245 #define MN_SOURCE_CLKS_MASK 0x3
246 
247 #endif /* __INTEL_DAI_DRIVER_SSP_REGSV1_H__ */
248