1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * SD card specification 9 */ 10 11 #ifndef ZEPHYR_SUBSYS_SD_SPEC_H_ 12 #define ZEPHYR_SUBSYS_SD_SPEC_H_ 13 14 #include <stdint.h> 15 #include <zephyr/sys/util.h> 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /** 22 * @brief SD specification command opcodes 23 * 24 * SD specification command opcodes. Note that some command opcodes are 25 * specific to SDIO cards, or cards running in SPI mode instead of native SD 26 * mode. 27 */ 28 enum sd_opcode { 29 SD_GO_IDLE_STATE = 0, 30 MMC_SEND_OP_COND = 1, 31 SD_ALL_SEND_CID = 2, 32 SD_SEND_RELATIVE_ADDR = 3, 33 MMC_SEND_RELATIVE_ADDR = 3, 34 SDIO_SEND_OP_COND = 5, /* SDIO cards only */ 35 SD_SWITCH = 6, 36 SD_SELECT_CARD = 7, 37 SD_SEND_IF_COND = 8, 38 MMC_SEND_EXT_CSD = 8, 39 SD_SEND_CSD = 9, 40 SD_SEND_CID = 10, 41 SD_VOL_SWITCH = 11, 42 SD_STOP_TRANSMISSION = 12, 43 SD_SEND_STATUS = 13, 44 MMC_CHECK_BUS_TEST = 14, 45 SD_GO_INACTIVE_STATE = 15, 46 SD_SET_BLOCK_SIZE = 16, 47 SD_READ_SINGLE_BLOCK = 17, 48 SD_READ_MULTIPLE_BLOCK = 18, 49 SD_SEND_TUNING_BLOCK = 19, 50 MMC_SEND_BUS_TEST = 19, 51 MMC_SEND_TUNING_BLOCK = 21, 52 SD_SET_BLOCK_COUNT = 23, 53 SD_WRITE_SINGLE_BLOCK = 24, 54 SD_WRITE_MULTIPLE_BLOCK = 25, 55 SD_ERASE_BLOCK_START = 32, 56 SD_ERASE_BLOCK_END = 33, 57 SD_ERASE_BLOCK_OPERATION = 38, 58 SDIO_RW_DIRECT = 52, 59 SDIO_RW_EXTENDED = 53, 60 SD_APP_CMD = 55, 61 SD_SPI_READ_OCR = 58, /* SPI mode only */ 62 SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ 63 }; 64 65 /** 66 * @brief SD application command opcodes. 67 * 68 * all application command opcodes must be prefixed with a CMD55 command 69 * to inform the SD card the next command is an application-specific one. 70 */ 71 enum sd_app_cmd { 72 SD_APP_SET_BUS_WIDTH = 6, 73 SD_APP_SEND_STATUS = 13, 74 SD_APP_SEND_NUM_WRITTEN_BLK = 22, 75 SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, 76 SD_APP_SEND_OP_COND = 41, 77 SD_APP_CLEAR_CARD_DETECT = 42, 78 SD_APP_SEND_SCR = 51, 79 }; 80 81 /** 82 * @brief Native SD mode R1 response status flags 83 * 84 * Native response flags for SD R1 response, used to check for error in command. 85 */ 86 enum sd_r1_status { 87 /* Bits 0-2 reserved */ 88 SD_R1_AUTH_ERR = BIT(3), 89 /* Bit 4 reserved for SDIO */ 90 SD_R1_APP_CMD = BIT(5), 91 SD_R1_FX_EVENT = BIT(6), 92 /* Bit 7 reserved */ 93 SD_R1_RDY_DATA = BIT(8), 94 SD_R1_CUR_STATE = (0xFU << 9), 95 SD_R1_ERASE_RESET = BIT(13), 96 SD_R1_ECC_DISABLED = BIT(14), 97 SD_R1_ERASE_SKIP = BIT(15), 98 SD_R1_CSD_OVERWRITE = BIT(16), 99 /* Bits 17-18 reserved */ 100 SD_R1_ERR = BIT(19), 101 SD_R1_CC_ERR = BIT(20), 102 SD_R1_ECC_FAIL = BIT(21), 103 SD_R1_ILLEGAL_CMD = BIT(22), 104 SD_R1_CRC_ERR = BIT(23), 105 SD_R1_UNLOCK_FAIL = BIT(24), 106 SD_R1_CARD_LOCKED = BIT(25), 107 SD_R1_WP_VIOLATION = BIT(26), 108 SD_R1_ERASE_PARAM = BIT(27), 109 SD_R1_ERASE_SEQ_ERR = BIT(28), 110 SD_R1_BLOCK_LEN_ERR = BIT(29), 111 SD_R1_ADDR_ERR = BIT(30), 112 SD_R1_OUT_OF_RANGE = BIT(31), 113 SD_R1_ERR_FLAGS = (SD_R1_AUTH_ERR | 114 SD_R1_ERASE_SKIP | 115 SD_R1_CSD_OVERWRITE | 116 SD_R1_ERR | 117 SD_R1_CC_ERR | 118 SD_R1_ECC_FAIL | 119 SD_R1_ILLEGAL_CMD | 120 SD_R1_CRC_ERR | 121 SD_R1_UNLOCK_FAIL | 122 SD_R1_WP_VIOLATION | 123 SD_R1_ERASE_PARAM | 124 SD_R1_ERASE_SEQ_ERR | 125 SD_R1_BLOCK_LEN_ERR | 126 SD_R1_ADDR_ERR | 127 SD_R1_OUT_OF_RANGE), 128 SD_R1ERR_NONE = 0, 129 }; 130 131 #define SD_R1_CURRENT_STATE(x) (((x) & SD_R1_CUR_STATE) >> 9U) 132 133 /** 134 * @brief SD current state values 135 * 136 * SD current state values, contained in R1 response data. 137 */ 138 enum sd_r1_current_state { 139 SDMMC_R1_IDLE = 0U, 140 SDMMC_R1_READY = 1U, 141 SDMMC_R1_IDENTIFY = 2U, 142 SDMMC_R1_STANDBY = 3U, 143 SDMMC_R1_TRANSFER = 4U, 144 SDMMC_R1_SEND_DATA = 5U, 145 SDMMC_R1_RECIVE_DATA = 6U, 146 SDMMC_R1_PROGRAM = 7U, 147 SDMMC_R1_DISCONNECT = 8U, 148 }; 149 150 /** 151 * @brief SPI SD mode R1 response status flags 152 * 153 * SPI mode R1 response flags. Used to check for error in SD SPI mode command. 154 */ 155 enum sd_spi_r1_error_flag { 156 SD_SPI_R1PARAMETER_ERR = BIT(6), 157 SD_SPI_R1ADDRESS_ERR = BIT(5), 158 SD_SPI_R1ERASE_SEQ_ERR = BIT(4), 159 SD_SPI_R1CMD_CRC_ERR = BIT(3), 160 SD_SPI_R1ILLEGAL_CMD_ERR = BIT(2), 161 SD_SPI_R1ERASE_RESET = BIT(1), 162 SD_SPI_R1IDLE_STATE = BIT(0), 163 }; 164 165 /** 166 * @brief SPI SD mode R2 response status flags 167 * 168 * SPI mode R2 response flags. Sent in response to SEND_STATUS command. Used 169 * to check status of SD card. 170 */ 171 enum sd_spi_r2_status { 172 SDHC_SPI_R2_CARD_LOCKED = BIT(8), 173 SDHC_SPI_R2_UNLOCK_FAIL = BIT(9), 174 SDHC_SPI_R2_ERR = BIT(10), 175 SDHC_SPI_R2_CC_ERR = BIT(11), 176 SDHC_SPI_R2_ECC_FAIL = BIT(12), 177 SDHC_SPI_R2_WP_VIOLATION = BIT(13), 178 SDHC_SPI_R2_ERASE_PARAM = BIT(14), 179 SDHC_SPI_R2_OUT_OF_RANGE = BIT(15), 180 }; 181 182 /* Byte length of SD SPI mode command */ 183 #define SD_SPI_CMD_SIZE 6 184 #define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1) 185 /* Byte length of CRC16 appended to data blocks in SPI mode */ 186 #define SD_SPI_CRC16_SIZE 2 187 188 /* SPI Command flags */ 189 #define SD_SPI_START 0x80 190 #define SD_SPI_TX 0x40 191 #define SD_SPI_CMD 0x3F 192 193 /* SPI Data block tokens */ 194 #define SD_SPI_TOKEN_SINGLE 0xFE 195 #define SD_SPI_TOKEN_MULTI_WRITE 0xFC 196 #define SD_SPI_TOKEN_STOP_TRAN 0xFD 197 198 /* SPI Data block responses */ 199 #define SD_SPI_RESPONSE_ACCEPTED 0x05 200 #define SD_SPI_RESPONSE_CRC_ERR 0x0B 201 #define SD_SPI_RESPONSE_WRITE_ERR 0x0C 202 203 /* Masks used in SD interface condition query (CMD8) */ 204 #define SD_IF_COND_VHS_MASK (0x0F << 8) 205 #define SD_IF_COND_VHS_3V3 BIT(8) 206 #define SD_IF_COND_CHECK 0xAA 207 208 /** 209 * @brief SD response types 210 * 211 * SD response types. Note that SPI mode has difference response types than 212 * cards in native SD mode. 213 */ 214 enum sd_rsp_type { 215 /* Native response types (lower 4 bits) */ 216 SD_RSP_TYPE_NONE = 0U, 217 SD_RSP_TYPE_R1 = 1U, 218 SD_RSP_TYPE_R1b = 2U, 219 SD_RSP_TYPE_R2 = 3U, 220 SD_RSP_TYPE_R3 = 4U, 221 SD_RSP_TYPE_R4 = 5U, 222 SD_RSP_TYPE_R5 = 6U, 223 SD_RSP_TYPE_R5b = 7U, 224 SD_RSP_TYPE_R6 = 8U, 225 SD_RSP_TYPE_R7 = 9U, 226 /* SPI response types (bits [7:4]) */ 227 SD_SPI_RSP_TYPE_R1 = (1U << 4), 228 SD_SPI_RSP_TYPE_R1b = (2U << 4), 229 SD_SPI_RSP_TYPE_R2 = (3U << 4), 230 SD_SPI_RSP_TYPE_R3 = (4U << 4), 231 SD_SPI_RSP_TYPE_R4 = (5U << 4), 232 SD_SPI_RSP_TYPE_R5 = (6U << 4), 233 SD_SPI_RSP_TYPE_R7 = (7U << 4), 234 }; 235 236 /** 237 * @brief SD support flags 238 * 239 * flags used by SD subsystem to determine support for SD card features. 240 */ 241 enum sd_support_flag { 242 SD_HIGH_CAPACITY_FLAG = BIT(1), 243 SD_4BITS_WIDTH = BIT(2), 244 SD_SDHC_FLAG = BIT(3), 245 SD_SDXC_FLAG = BIT(4), 246 SD_1800MV_FLAG = BIT(5), 247 SD_3000MV_FLAG = BIT(6), 248 SD_CMD23_FLAG = BIT(7), 249 SD_SPEED_CLASS_CONTROL_FLAG = BIT(8), 250 SD_MEM_PRESENT_FLAG = BIT(9), 251 }; 252 253 254 /** 255 * @brief SD OCR bit flags 256 * 257 * bit flags present in SD OCR response. Used to determine status and 258 * supported functions of SD card. 259 */ 260 enum sd_ocr_flag { 261 /** Power up busy status */ 262 SD_OCR_PWR_BUSY_FLAG = BIT(31), 263 /** Card capacity status */ 264 SD_OCR_HOST_CAP_FLAG = BIT(30), 265 /** Card capacity status */ 266 SD_OCR_CARD_CAP_FLAG = SD_OCR_HOST_CAP_FLAG, 267 /** Switch to 1.8V request */ 268 SD_OCR_SWITCH_18_REQ_FLAG = BIT(24), 269 /** Switch to 1.8V accepted */ 270 SD_OCR_SWITCH_18_ACCEPT_FLAG = SD_OCR_SWITCH_18_REQ_FLAG, 271 /** VDD 2.7-2.8 */ 272 SD_OCR_VDD27_28FLAG = BIT(15), 273 /** VDD 2.8-2.9 */ 274 SD_OCR_VDD28_29FLAG = BIT(16), 275 /** VDD 2.9-3.0 */ 276 SD_OCR_VDD29_30FLAG = BIT(17), 277 /** VDD 3.0-3.1 */ 278 SD_OCR_VDD30_31FLAG = BIT(18), 279 /** VDD 3.1-3.2 */ 280 SD_OCR_VDD31_32FLAG = BIT(19), 281 /** VDD 3.2-3.3 */ 282 SD_OCR_VDD32_33FLAG = BIT(20), 283 /** VDD 3.3-3.4 */ 284 SD_OCR_VDD33_34FLAG = BIT(21), 285 /** VDD 3.4-3.5 */ 286 SD_OCR_VDD34_35FLAG = BIT(22), 287 /** VDD 3.5-3.6 */ 288 SD_OCR_VDD35_36FLAG = BIT(23), 289 }; 290 291 /** 292 * @brief MMC OCR bit flags 293 * 294 * bit flags present in MMC OCR response. Used to determine status and 295 * supported functions of MMC card. 296 */ 297 enum mmc_ocr_flag { 298 MMC_OCR_VDD170_195FLAG = BIT(7), 299 MMC_OCR_VDD20_26FLAG = 0x7F << 8, 300 MMC_OCR_VDD27_36FLAG = 0x1FF << 15, 301 MMC_OCR_SECTOR_MODE = BIT(30), 302 MMC_OCR_PWR_BUSY_FLAG = BIT(31) 303 }; 304 305 #define SDIO_OCR_IO_NUMBER_SHIFT 28 306 /* Lower 24 bits hold SDIO I/O OCR */ 307 #define SDIO_IO_OCR_MASK 0xFFFFFF 308 309 /** 310 * @brief SDIO OCR bit flags 311 * 312 * bit flags present in SDIO OCR response. Used to determine status and 313 * supported functions of SDIO card. 314 */ 315 enum sdio_ocr_flag { 316 SDIO_OCR_IO_READY_FLAG = BIT(31), 317 SDIO_OCR_IO_NUMBER = (7U << 28U), /*!< Number of io function */ 318 SDIO_OCR_MEM_PRESENT_FLAG = BIT(27), /*!< Memory present flag */ 319 SDIO_OCR_180_VOL_FLAG = BIT(24), /*!< Switch to 1.8v signalling */ 320 SDIO_OCR_VDD20_21FLAG = BIT(8), /*!< VDD 2.0-2.1 */ 321 SDIO_OCR_VDD21_22FLAG = BIT(9), /*!< VDD 2.1-2.2 */ 322 SDIO_OCR_VDD22_23FLAG = BIT(10), /*!< VDD 2.2-2.3 */ 323 SDIO_OCR_VDD23_24FLAG = BIT(11), /*!< VDD 2.3-2.4 */ 324 SDIO_OCR_VDD24_25FLAG = BIT(12), /*!< VDD 2.4-2.5 */ 325 SDIO_OCR_VDD25_26FLAG = BIT(13), /*!< VDD 2.5-2.6 */ 326 SDIO_OCR_VDD26_27FLAG = BIT(14), /*!< VDD 2.6-2.7 */ 327 SDIO_OCR_VDD27_28FLAG = BIT(15), /*!< VDD 2.7-2.8 */ 328 SDIO_OCR_VDD28_29FLAG = BIT(16), /*!< VDD 2.8-2.9 */ 329 SDIO_OCR_VDD29_30FLAG = BIT(17), /*!< VDD 2.9-3.0 */ 330 SDIO_OCR_VDD30_31FLAG = BIT(18), /*!< VDD 2.9-3.0 */ 331 SDIO_OCR_VDD31_32FLAG = BIT(19), /*!< VDD 3.0-3.1 */ 332 SDIO_OCR_VDD32_33FLAG = BIT(20), /*!< VDD 3.1-3.2 */ 333 SDIO_OCR_VDD33_34FLAG = BIT(21), /*!< VDD 3.2-3.3 */ 334 SDIO_OCR_VDD34_35FLAG = BIT(22), /*!< VDD 3.3-3.4 */ 335 SDIO_OCR_VDD35_36FLAG = BIT(23), /*!< VDD 3.4-3.5 */ 336 }; 337 338 339 /** 340 * @brief SD switch arguments 341 * 342 * SD CMD6 can either check or set a function. Bitfields are used to indicate 343 * feature support when checking a function, and when setting a function an 344 * integer value is used to select it. 345 */ 346 enum sd_switch_arg { 347 /** SD switch mode 0: check function */ 348 SD_SWITCH_CHECK = 0U, 349 /** SD switch mode 1: set function */ 350 SD_SWITCH_SET = 1U, 351 }; 352 353 /** 354 * @brief SD switch group numbers 355 * 356 * SD CMD6 has multiple function groups it can check/set. These indicies are 357 * used to determine which group CMD6 will interact with. 358 */ 359 enum sd_group_num { 360 /** access mode group */ 361 SD_GRP_TIMING_MODE = 0U, 362 /** command system group */ 363 SD_GRP_CMD_SYS_MODE = 1U, 364 /** driver strength group */ 365 SD_GRP_DRIVER_STRENGTH_MODE = 2U, 366 /** current limit group */ 367 SD_GRP_CURRENT_LIMIT_MODE = 3U, 368 }; 369 370 /* Maximum data rate possible for SD high speed cards */ 371 enum hs_max_data_rate { 372 HS_UNSUPPORTED = 0, 373 HS_MAX_DTR = MHZ(50), 374 }; 375 376 /* Maximum data rate possible for SD uhs cards */ 377 enum uhs_max_data_rate { 378 UHS_UNSUPPORTED = 0, 379 UHS_SDR12_MAX_DTR = MHZ(25), 380 UHS_SDR25_MAX_DTR = MHZ(50), 381 UHS_SDR50_MAX_DTR = MHZ(100), 382 UHS_SDR104_MAX_DTR = MHZ(208), 383 UHS_DDR50_MAX_DTR = MHZ(50), 384 }; 385 386 /** 387 * @brief SD bus speed support bit flags 388 * 389 * Bit flags indicating support for SD bus speeds. 390 * these bit flags are provided as a response to CMD6 by the card 391 */ 392 enum sd_bus_speed { 393 UHS_SDR12_BUS_SPEED = BIT(0), 394 DEFAULT_BUS_SPEED = BIT(0), 395 HIGH_SPEED_BUS_SPEED = BIT(1), 396 UHS_SDR25_BUS_SPEED = BIT(1), 397 UHS_SDR50_BUS_SPEED = BIT(2), 398 UHS_SDR104_BUS_SPEED = BIT(3), 399 UHS_DDR50_BUS_SPEED = BIT(4), 400 }; 401 402 /** 403 * @brief SD timing mode function selection values. 404 * 405 * sent to the card via CMD6 to select a card speed, and used by SD host 406 * controller to identify timing of card. 407 */ 408 enum sd_timing_mode { 409 /** Default Mode */ 410 SD_TIMING_DEFAULT = 0U, 411 /** SDR12 mode */ 412 SD_TIMING_SDR12 = 0U, 413 /** High speed mode */ 414 SD_TIMING_HIGH_SPEED = 1U, 415 /** SDR25 mode */ 416 SD_TIMING_SDR25 = 1U, 417 /** SDR50 mode*/ 418 SD_TIMING_SDR50 = 2U, 419 /** SDR104 mode */ 420 SD_TIMING_SDR104 = 3U, 421 /** DDR50 mode */ 422 SD_TIMING_DDR50 = 4U, 423 }; 424 425 /** 426 * @brief SD host controller clock speed 427 * 428 * Controls the SD host controller clock speed on the SD bus. 429 */ 430 enum sdhc_clock_speed { 431 SDMMC_CLOCK_400KHZ = KHZ(400), 432 SD_CLOCK_25MHZ = MHZ(25), 433 SD_CLOCK_50MHZ = MHZ(50), 434 SD_CLOCK_100MHZ = MHZ(100), 435 SD_CLOCK_208MHZ = MHZ(208), 436 MMC_CLOCK_26MHZ = MHZ(26), 437 MMC_CLOCK_52MHZ = MHZ(52), 438 MMC_CLOCK_DDR52 = MHZ(52), 439 MMC_CLOCK_HS200 = MHZ(200), 440 MMC_CLOCK_HS400 = MHZ(200), /* Same clock freq as HS200, just DDR */ 441 }; 442 443 /** 444 * @brief SD current setting values 445 * 446 * Used with CMD6 to inform the card what its maximum current draw is. 447 */ 448 enum sd_current_setting { 449 SD_SET_CURRENT_200MA = 0, 450 SD_SET_CURRENT_400MA = 1, 451 SD_SET_CURRENT_600MA = 2, 452 SD_SET_CURRENT_800MA = 3, 453 }; 454 455 /** 456 * @brief SD current support bitfield 457 * 458 * Used with CMD6 to determine the maximum current the card will draw. 459 */ 460 enum sd_current_limit { 461 /** default current limit */ 462 SD_MAX_CURRENT_200MA = BIT(0), 463 /** current limit to 400MA */ 464 SD_MAX_CURRENT_400MA = BIT(1), 465 /** current limit to 600MA */ 466 SD_MAX_CURRENT_600MA = BIT(2), 467 /** current limit to 800MA */ 468 SD_MAX_CURRENT_800MA = BIT(3), 469 }; 470 471 /** 472 * @brief SD driver types 473 * 474 * Used with CMD6 to determine the driver type the card should use. 475 */ 476 enum sd_driver_type { 477 SD_DRIVER_TYPE_B = 0x1, 478 SD_DRIVER_TYPE_A = 0x2, 479 SD_DRIVER_TYPE_C = 0x4, 480 SD_DRIVER_TYPE_D = 0x8, 481 }; 482 483 /** 484 * @brief SD switch drive type selection 485 * 486 * These values are used to select the preferred driver type for an SD card. 487 */ 488 enum sd_driver_strength { 489 /** default driver strength*/ 490 SD_DRV_STRENGTH_TYPEB = 0U, 491 /** driver strength TYPE A */ 492 SD_DRV_STRENGTH_TYPEA = 1U, 493 /** driver strength TYPE C */ 494 SD_DRV_STRENGTH_TYPEC = 2U, 495 /** driver strength TYPE D */ 496 SD_DRV_STRENGTH_TYPED = 3U, 497 }; 498 499 /** 500 * @brief SD switch capabilities 501 * 502 * records switch capabilities for SD card. These capabilities are set 503 * and queried via CMD6 504 */ 505 struct sd_switch_caps { 506 enum hs_max_data_rate hs_max_dtr; 507 enum uhs_max_data_rate uhs_max_dtr; 508 enum sd_bus_speed bus_speed; 509 enum sd_driver_type sd_drv_type; 510 enum sd_current_limit sd_current_limit; 511 }; 512 513 514 #define SD_PRODUCT_NAME_BYTES 5 515 516 /** 517 * @brief SD card identification register 518 * 519 * Layout of SD card identification register 520 */ 521 struct sd_cid { 522 /** Manufacturer ID [127:120] */ 523 uint8_t manufacturer; 524 /** OEM/Application ID [119:104] */ 525 uint16_t application; 526 /** Product name [103:64] */ 527 uint8_t name[SD_PRODUCT_NAME_BYTES]; 528 /** Product revision [63:56] */ 529 uint8_t version; 530 /** Product serial number [55:24] */ 531 uint32_t ser_num; 532 /** Manufacturing date [19:8] */ 533 uint16_t date; 534 }; 535 536 /** 537 * @brief SD card specific data register. 538 * 539 * Card specific data register. contains additional data about SD card. 540 */ 541 struct sd_csd { 542 /** CSD structure [127:126] */ 543 uint8_t csd_structure; 544 /** Data read access-time-1 [119:112] */ 545 uint8_t read_time1; 546 /** Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ 547 uint8_t read_time2; 548 /** Maximum data transfer rate [103:96] */ 549 uint8_t xfer_rate; 550 /** Card command classes [95:84] */ 551 uint16_t cmd_class; 552 /** Maximum read data block length [83:80] */ 553 uint8_t read_blk_len; 554 /** Flags in _sd_csd_flag */ 555 uint16_t flags; 556 /** Device size [73:62] */ 557 uint32_t device_size; 558 /** Maximum read current at VDD min [61:59] */ 559 uint8_t read_current_min; 560 /** Maximum read current at VDD max [58:56] */ 561 uint8_t read_current_max; 562 /** Maximum write current at VDD min [55:53] */ 563 uint8_t write_current_min; 564 /** Maximum write current at VDD max [52:50] */ 565 uint8_t write_current_max; 566 /** Device size multiplier [49:47] */ 567 uint8_t dev_size_mul; 568 /** Erase sector size [45:39] */ 569 uint8_t erase_size; 570 /** Write protect group size [38:32] */ 571 uint8_t write_prtect_size; 572 /** Write speed factor [28:26] */ 573 uint8_t write_speed_factor; 574 /** Maximum write data block length [25:22] */ 575 uint8_t write_blk_len; 576 /** File format [11:10] */ 577 uint8_t file_fmt; 578 }; 579 580 /** 581 * @brief MMC Maximum Frequency 582 * 583 * Max freq in MMC csd 584 */ 585 enum mmc_csd_freq { 586 MMC_MAXFREQ_100KHZ = 0U << 0U, 587 MMC_MAXFREQ_1MHZ = 1U << 0U, 588 MMC_MAXFREQ_10MHZ = 2U << 0U, 589 MMC_MAXFREQ_100MHZ = 3U << 0U, 590 MMC_MAXFREQ_MULT_10 = 1U << 3U, 591 MMC_MAXFREQ_MULT_12 = 2U << 3U, 592 MMC_MAXFREQ_MULT_13 = 3U << 3U, 593 MMC_MAXFREQ_MULT_15 = 4U << 3U, 594 MMC_MAXFREQ_MULT_20 = 5U << 3U, 595 MMC_MAXFREQ_MULT_26 = 6U << 3U, 596 MMC_MAXFREQ_MULT_30 = 7U << 3U, 597 MMC_MAXFREQ_MULT_35 = 8U << 3U, 598 MMC_MAXFREQ_MULT_40 = 9U << 3U, 599 MMC_MAXFREQ_MULT_45 = 0xAU << 3U, 600 MMC_MAXFREQ_MULT_52 = 0xBU << 3U, 601 MMC_MAXFREQ_MULT_55 = 0xCU << 3U, 602 MMC_MAXFREQ_MULT_60 = 0xDU << 3U, 603 MMC_MAXFREQ_MULT_70 = 0xEU << 3U, 604 MMC_MAXFREQ_MULT_80 = 0xFU << 3u 605 }; 606 607 /** 608 * @brief MMC Timing Modes 609 * 610 * MMC Timing Mode, encoded in EXT_CSD 611 */ 612 enum mmc_timing_mode { 613 MMC_LEGACY_TIMING = 0U, 614 MMC_HS_TIMING = 1U, 615 MMC_HS200_TIMING = 2U, 616 MMC_HS400_TIMING = 3U 617 }; 618 619 /** 620 * @brief MMC Driver Strengths 621 * 622 * Encoded in EXT_CSD 623 */ 624 enum mmc_driver_strengths { 625 mmc_driv_type0 = 0U, 626 mmc_driv_type1 = 1U, 627 mmc_driv_type2 = 2U, 628 mmc_driv_type3 = 3U, 629 mmc_driv_type4 = 4U 630 }; 631 632 633 /** 634 * @brief MMC Device Type 635 * 636 * Encoded in EXT_CSD 637 */ 638 struct mmc_device_type { 639 bool MMC_HS400_DDR_1200MV; 640 bool MMC_HS400_DDR_1800MV; 641 bool MMC_HS200_SDR_1200MV; 642 bool MMC_HS200_SDR_1800MV; 643 bool MMC_HS_DDR_1200MV; 644 bool MMC_HS_DDR_1800MV; 645 bool MMC_HS_52_DV; 646 bool MMC_HS_26_DV; 647 }; 648 649 /** 650 * @brief CSD Revision 651 * 652 * Value of CSD rev in EXT_CSD 653 */ 654 enum mmc_ext_csd_rev { 655 MMC_5_1 = 8U, 656 MMC_5_0 = 7U, 657 MMC_4_5 = 6U, 658 MMC_4_4 = 5U, 659 MMC_4_3 = 3U, 660 MMC_4_2 = 2U, 661 MMC_4_1 = 1U, 662 MMC_4_0 = 0U 663 }; 664 665 /** 666 * @brief MMC extended card specific data register 667 * 668 * Extended card specific data register. 669 * Contains additional additional data about MMC card. 670 */ 671 struct mmc_ext_csd { 672 /** Sector Count [215:212] */ 673 uint32_t sec_count; 674 /** Bus Width Mode [183] */ 675 uint8_t bus_width; 676 /** High Speed Timing Mode [185] */ 677 enum mmc_timing_mode hs_timing; 678 /** Device Type [196] */ 679 struct mmc_device_type device_type; 680 /** Extended CSD Revision [192] */ 681 enum mmc_ext_csd_rev rev; 682 /** Selected power class [187]*/ 683 uint8_t power_class; 684 /** Driver strengths [197] */ 685 uint8_t mmc_driver_strengths; 686 /** Power class information for HS200 at VCC!=1.95V [237] */ 687 uint8_t pwr_class_200MHZ_VCCQ195; 688 /** Power class information for HS400 [253] */ 689 uint8_t pwr_class_HS400; 690 /** Size of eMMC cache [252:249] */ 691 uint32_t cache_size; 692 }; 693 694 /** 695 * @brief SD card specific data flags 696 * 697 * flags used in decoding the SD card specific data register 698 */ 699 enum sd_csd_flag { 700 /** Partial blocks for read allowed [79:79] */ 701 SD_CSD_READ_BLK_PARTIAL_FLAG = BIT(0), 702 /** Write block misalignment [78:78] */ 703 SD_CSD_WRITE_BLK_MISALIGN_FLAG = BIT(1), 704 /** Read block misalignment [77:77] */ 705 SD_CSD_READ_BLK_MISALIGN_FLAG = BIT(2), 706 /** DSR implemented [76:76] */ 707 SD_CSD_DSR_IMPLEMENTED_FLAG = BIT(3), 708 /** Erase single block enabled [46:46] */ 709 SD_CSD_ERASE_BLK_EN_FLAG = BIT(4), 710 /** Write protect group enabled [31:31] */ 711 SD_CSD_WRITE_PROTECT_GRP_EN_FLAG = BIT(5), 712 /** Partial blocks for write allowed [21:21] */ 713 SD_CSD_WRITE_BLK_PARTIAL_FLAG = BIT(6), 714 /** File format group [15:15] */ 715 SD_CSD_FILE_FMT_GRP_FLAG = BIT(7), 716 /** Copy flag [14:14] */ 717 SD_CSD_COPY_FLAG = BIT(8), 718 /** Permanent write protection [13:13] */ 719 SD_CSD_PERMANENT_WRITE_PROTECT_FLAG = BIT(9), 720 /** Temporary write protection [12:12] */ 721 SD_CSD_TMP_WRITE_PROTECT_FLAG = BIT(10), 722 }; 723 724 /** 725 * @brief SD card configuration register 726 * 727 * Even more SD card data. 728 */ 729 struct sd_scr { 730 /** SCR Structure [63:60] */ 731 uint8_t scr_structure; 732 /** SD memory card specification version [59:56] */ 733 uint8_t sd_spec; 734 /** SCR flags in _sd_scr_flag */ 735 uint16_t flags; 736 /** Security specification supported [54:52] */ 737 uint8_t sd_sec; 738 /** Data bus widths supported [51:48] */ 739 uint8_t sd_width; 740 /** Extended security support [46:43] */ 741 uint8_t sd_ext_sec; 742 /** Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ 743 uint8_t cmd_support; 744 /** reserved for manufacturer usage [31:0] */ 745 uint32_t rsvd; 746 }; 747 748 /** 749 * @brief SD card configuration register 750 * 751 * flags used in decoding the SD card configuration register 752 */ 753 enum sd_scr_flag { 754 /** Data status after erases [55:55] */ 755 SD_SCR_DATA_STATUS_AFTER_ERASE = BIT(0), 756 /** Specification version 3.00 or higher [47:47]*/ 757 SD_SCR_SPEC3 = BIT(1), 758 }; 759 760 /** 761 * @brief SD specification version 762 * 763 * SD spec version flags used in decoding the SD card configuration register 764 */ 765 enum sd_spec_version { 766 /** SD card version 1.0-1.01 */ 767 SD_SPEC_VER1_0 = BIT(0), 768 /** SD card version 1.10 */ 769 SD_SPEC_VER1_1 = BIT(1), 770 /** SD card version 2.00 */ 771 SD_SPEC_VER2_0 = BIT(2), 772 /** SD card version 3.0 */ 773 SD_SPEC_VER3_0 = BIT(3), 774 }; 775 776 777 #define SDMMC_DEFAULT_BLOCK_SIZE 512 778 #define MMC_EXT_CSD_BYTES 512 779 /** 780 * @brief SDIO function number 781 * 782 * SDIO function number used to select function when performing I/O on SDIO card 783 */ 784 enum sdio_func_num { 785 SDIO_FUNC_NUM_0 = 0, 786 SDIO_FUNC_NUM_1 = 1, 787 SDIO_FUNC_NUM_2 = 2, 788 SDIO_FUNC_NUM_3 = 3, 789 SDIO_FUNC_NUM_4 = 4, 790 SDIO_FUNC_NUM_5 = 5, 791 SDIO_FUNC_NUM_6 = 6, 792 SDIO_FUNC_NUM_7 = 7, 793 SDIO_FUNC_MEMORY = 8, 794 }; 795 796 /** 797 * @brief SDIO I/O direction 798 * 799 * SDIO I/O direction (read or write) 800 */ 801 enum sdio_io_dir { 802 SDIO_IO_READ = 0, 803 SDIO_IO_WRITE = 1, 804 }; 805 806 #define SDIO_CMD_ARG_RW_SHIFT 31 /*!< read/write flag shift */ 807 #define SDIO_CMD_ARG_FUNC_NUM_SHIFT 28 /*!< function number shift */ 808 #define SDIO_DIRECT_CMD_ARG_RAW_SHIFT 27 /*!< direct raw flag shift */ 809 #define SDIO_CMD_ARG_REG_ADDR_SHIFT 9 /*!< direct reg addr shift */ 810 #define SDIO_CMD_ARG_REG_ADDR_MASK 0x1FFFF /*!< direct reg addr mask */ 811 #define SDIO_DIRECT_CMD_DATA_MASK 0xFF /*!< data mask */ 812 813 #define SDIO_EXTEND_CMD_ARG_BLK_SHIFT 27 /*!< extended write block mode */ 814 #define SDIO_EXTEND_CMD_ARG_OP_CODE_SHIFT 26 /*!< op code (increment address) */ 815 816 /** 817 * @brief Card common control register definitions 818 * 819 * Card common control registers, present on all SDIO cards 820 */ 821 #define SDIO_CCCR_CCCR 0x00 /*!< SDIO CCCR revision register */ 822 #define SDIO_CCCR_CCCR_REV_MASK 0x0F 823 #define SDIO_CCCR_CCCR_REV_SHIFT 0x0 824 #define SDIO_CCCR_CCCR_REV_1_00 0x0 /*!< CCCR/FBR Version 1.00 */ 825 #define SDIO_CCCR_CCCR_REV_1_10 0x1 /*!< CCCR/FBR Version 1.10 */ 826 #define SDIO_CCCR_CCCR_REV_2_00 0x2 /*!< CCCR/FBR Version 2.00 */ 827 #define SDIO_CCCR_CCCR_REV_3_00 0x3 /*!< CCCR/FBR Version 3.00 */ 828 829 #define SDIO_CCCR_SD 0x01 /*!< SD spec version register */ 830 #define SDIO_CCCR_SD_SPEC_MASK 0x0F 831 #define SDIO_CCCR_SD_SPEC_SHIFT 0x0 832 833 #define SDIO_CCCR_IO_EN 0x02 /*!< SDIO IO Enable register */ 834 835 #define SDIO_CCCR_IO_RD 0x03 /*!< SDIO IO Ready register */ 836 837 #define SDIO_CCCR_INT_EN 0x04 /*!< SDIO Interrupt enable register */ 838 839 #define SDIO_CCCR_INT_P 0x05 /*!< SDIO Interrupt pending register */ 840 841 #define SDIO_CCCR_ABORT 0x06 /*!< SDIO IO abort register */ 842 843 #define SDIO_CCCR_BUS_IF 0x07 /*!< SDIO bus interface control register */ 844 #define SDIO_CCCR_BUS_IF_WIDTH_MASK 0x3 /*!< SDIO bus width setting mask */ 845 #define SDIO_CCCR_BUS_IF_WIDTH_1_BIT 0x00 /*!< 1 bit SDIO bus setting */ 846 #define SDIO_CCCR_BUS_IF_WIDTH_4_BIT 0x02 /*!< 4 bit SDIO bus setting */ 847 #define SDIO_CCCR_BUS_IF_WIDTH_8_BIT 0x03 /*!< 8 bit SDIO bus setting */ 848 849 #define SDIO_CCCR_CAPS 0x08 /*!< SDIO card capabilities */ 850 #define SDIO_CCCR_CAPS_SDC BIT(0) /*!< support CMD52 while data transfer */ 851 #define SDIO_CCCR_CAPS_SMB BIT(1) /*!< support multiple block transfer */ 852 #define SDIO_CCCR_CAPS_SRW BIT(2) /*!< support read wait control */ 853 #define SDIO_CCCR_CAPS_SBS BIT(3) /*!< support bus control */ 854 #define SDIO_CCCR_CAPS_S4MI BIT(4) /*!< support block gap interrupt */ 855 #define SDIO_CCCR_CAPS_E4MI BIT(5) /*!< enable block gap interrupt */ 856 #define SDIO_CCCR_CAPS_LSC BIT(6) /*!< low speed card */ 857 #define SDIO_CCCR_CAPS_BLS BIT(7) /*!< low speed card with 4 bit support */ 858 859 #define SDIO_CCCR_CIS 0x09 /*!< SDIO CIS tuples pointer */ 860 861 #define SDIO_CCCR_SPEED 0x13 /*!< SDIO bus speed select */ 862 #define SDIO_CCCR_SPEED_SHS BIT(0) /*!< high speed support */ 863 #define SDIO_CCCR_SPEED_MASK 0xE /*!< bus speed select mask*/ 864 #define SDIO_CCCR_SPEED_SHIFT 0x1 /*!< bus speed select shift */ 865 #define SDIO_CCCR_SPEED_SDR12 0x0 /*!< select SDR12 */ 866 #define SDIO_CCCR_SPEED_HS 0x1 /*!< select High speed mode */ 867 #define SDIO_CCCR_SPEED_SDR25 0x1 /*!< select SDR25 */ 868 #define SDIO_CCCR_SPEED_SDR50 0x2 /*!< select SDR50 */ 869 #define SDIO_CCCR_SPEED_SDR104 0x3 /*!< select SDR104 */ 870 #define SDIO_CCCR_SPEED_DDR50 0x4 /*!< select DDR50 */ 871 872 #define SDIO_CCCR_UHS 0x14 /*!< SDIO UHS support */ 873 #define SDIO_CCCR_UHS_SDR50 BIT(0) /*!< SDR50 support */ 874 #define SDIO_CCCR_UHS_SDR104 BIT(1) /*!< SDR104 support */ 875 #define SDIO_CCCR_UHS_DDR50 BIT(2) /*!< DDR50 support */ 876 877 #define SDIO_CCCR_DRIVE_STRENGTH 0x15 /*!< SDIO drive strength */ 878 #define SDIO_CCCR_DRIVE_STRENGTH_A BIT(0) /*!< drive type A */ 879 #define SDIO_CCCR_DRIVE_STRENGTH_C BIT(1) /*!< drive type C */ 880 #define SDIO_CCCR_DRIVE_STRENGTH_D BIT(2) /*!< drive type D */ 881 882 #define SDIO_FBR_BASE(n) ((n) * 0x100) /*!< Get function base register addr */ 883 884 #define SDIO_FBR_CIS 0x09 /*!< SDIO function base register CIS pointer */ 885 #define SDIO_FBR_CSA 0x0C /*!< SDIO function base register CSA pointer */ 886 #define SDIO_FBR_BLK_SIZE 0x10 /*!< SDIO function base register block size */ 887 888 889 #define SDIO_MAX_IO_NUMS 7 /*!< Maximum number of I/O functions for SDIO */ 890 891 #define SDIO_TPL_CODE_NULL 0x00 /*!< NULL CIS tuple code */ 892 #define SDIO_TPL_CODE_MANIFID 0x20 /*!< manufacturer ID CIS tuple code */ 893 #define SDIO_TPL_CODE_FUNCID 0x21 /*!< function ID CIS tuple code */ 894 #define SDIO_TPL_CODE_FUNCE 0x22 /*!< function extension CIS tuple code */ 895 #define SDIO_TPL_CODE_END 0xFF /*!< End CIS tuple code */ 896 897 /** 898 * @brief Card common control register flags 899 * 900 * flags to indicate capabilities supported by an SDIO card, read from the CCCR 901 * registers 902 */ 903 enum sdio_cccr_flags { 904 SDIO_SUPPORT_HS = BIT(0), 905 SDIO_SUPPORT_SDR50 = BIT(1), 906 SDIO_SUPPORT_SDR104 = BIT(2), 907 SDIO_SUPPORT_DDR50 = BIT(3), 908 SDIO_SUPPORT_4BIT_LS_BUS = BIT(4), 909 SDIO_SUPPORT_MULTIBLOCK = BIT(5), 910 }; 911 912 /** 913 * @brief SDIO common CIS tuple properties 914 * 915 * CIS tuple properties. Note that additional properties exist for 916 * functions 1-7, but we do not read this data as the stack does not utilize it. 917 */ 918 struct sdio_cis { 919 /* Manufacturer ID string tuple */ 920 uint16_t manf_id; /*!< manufacturer ID */ 921 uint16_t manf_code; /*!< manufacturer code */ 922 /* Function identification tuple */ 923 uint8_t func_id; /*!< sdio device class function id */ 924 /* Function extension table */ 925 uint16_t max_blk_size; /*!< Max transfer block size */ 926 uint8_t max_speed; /*!< Max transfer speed */ 927 uint16_t rdy_timeout; /*!< I/O ready timeout */ 928 }; 929 930 #ifdef __cplusplus 931 } 932 #endif 933 934 #endif /* ZEPHYR_SUBSYS_SD_SPEC_H_ */ 935
