1 /*
2 * Copyright (c) 2021 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rcar_scif
8
9 #include <errno.h>
10 #include <zephyr/device.h>
11 #include <zephyr/devicetree.h>
12 #include <zephyr/drivers/uart.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/irq.h>
17 #include <zephyr/spinlock.h>
18
19 struct uart_rcar_cfg {
20 DEVICE_MMIO_ROM; /* Must be first */
21 const struct device *clock_dev;
22 struct rcar_cpg_clk mod_clk;
23 struct rcar_cpg_clk bus_clk;
24 const struct pinctrl_dev_config *pcfg;
25 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
26 void (*irq_config_func)(const struct device *dev);
27 #endif
28 bool is_hscif;
29 };
30
31 struct uart_rcar_data {
32 DEVICE_MMIO_RAM; /* Must be first */
33 struct uart_config current_config;
34 uint32_t clk_rate;
35 struct k_spinlock lock;
36 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
37 uart_irq_callback_user_data_t callback;
38 void *cb_data;
39 #endif
40 };
41
42 /* Registers */
43 #define SCSMR 0x00 /* Serial Mode Register */
44 #define SCBRR 0x04 /* Bit Rate Register */
45 #define SCSCR 0x08 /* Serial Control Register */
46 #define SCFTDR 0x0c /* Transmit FIFO Data Register */
47 #define SCFSR 0x10 /* Serial Status Register */
48 #define SCFRDR 0x14 /* Receive FIFO Data Register */
49 #define SCFCR 0x18 /* FIFO Control Register */
50 #define SCFDR 0x1c /* FIFO Data Count Register */
51 #define SCSPTR 0x20 /* Serial Port Register */
52 #define SCLSR 0x24 /* Line Status Register */
53 #define DL 0x30 /* Frequency Division Register */
54 #define CKS 0x34 /* Clock Select Register */
55 #define HSSRR 0x40 /* Sampling Rate Register */
56
57 /* SCSMR (Serial Mode Register) */
58 #define SCSMR_C_A BIT(7) /* Communication Mode */
59 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
60 #define SCSMR_PE BIT(5) /* Parity Enable */
61 #define SCSMR_O_E BIT(4) /* Odd Parity */
62 #define SCSMR_STOP BIT(3) /* Stop Bit Length */
63 #define SCSMR_CKS1 BIT(1) /* Clock Select 1 */
64 #define SCSMR_CKS0 BIT(0) /* Clock Select 0 */
65
66 /* SCSCR (Serial Control Register) */
67 #define SCSCR_TEIE BIT(11) /* Transmit End Interrupt Enable */
68 #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */
69 #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */
70 #define SCSCR_TE BIT(5) /* Transmit Enable */
71 #define SCSCR_RE BIT(4) /* Receive Enable */
72 #define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable */
73 #define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable */
74 #define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */
75 #define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */
76
77 /* SCFCR (FIFO Control Register) */
78 #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger 1 */
79 #define SCFCR_RTRG0 BIT(6) /* Receive FIFO Data Count Trigger 0 */
80 #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger 1 */
81 #define SCFCR_TTRG0 BIT(4) /* Transmit FIFO Data Count Trigger 0 */
82 #define SCFCR_MCE BIT(3) /* Modem Control Enable */
83 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
84 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
85 #define SCFCR_LOOP BIT(0) /* Loopback Test */
86
87 /* SCFSR (Serial Status Register) */
88 #define SCFSR_PER3 BIT(15) /* Parity Error Count 3 */
89 #define SCFSR_PER2 BIT(14) /* Parity Error Count 2 */
90 #define SCFSR_PER1 BIT(13) /* Parity Error Count 1 */
91 #define SCFSR_PER0 BIT(12) /* Parity Error Count 0 */
92 #define SCFSR_FER3 BIT(11) /* Framing Error Count 3 */
93 #define SCFSR_FER2 BIT(10) /* Framing Error Count 2 */
94 #define SCFSR_FER_1 BIT(9) /* Framing Error Count 1 */
95 #define SCFSR_FER0 BIT(8) /* Framing Error Count 0 */
96 #define SCFSR_ER BIT(7) /* Receive Error */
97 #define SCFSR_TEND BIT(6) /* Transmission ended */
98 #define SCFSR_TDFE BIT(5) /* Transmit FIFO Data Empty */
99 #define SCFSR_BRK BIT(4) /* Break Detect */
100 #define SCFSR_FER BIT(3) /* Framing Error */
101 #define SCFSR_PER BIT(2) /* Parity Error */
102 #define SCFSR_RDF BIT(1) /* Receive FIFO Data Full */
103 #define SCFSR_DR BIT(0) /* Receive Data Ready */
104
105 /* SCLSR (Line Status Register) on (H)SCIF */
106 #define SCLSR_TO BIT(2) /* Timeout */
107 #define SCLSR_ORER BIT(0) /* Overrun Error */
108
109 /* HSSRR (Sampling Rate Register) */
110 #define HSSRR_SRE BIT(15) /* Sampling Rate Register Enable */
111 #define HSSRR_SRCYC_DEF_VAL 0x7 /* Sampling rate default value */
112
uart_rcar_read_8(const struct device * dev,uint32_t offs)113 static uint8_t uart_rcar_read_8(const struct device *dev, uint32_t offs)
114 {
115 return sys_read8(DEVICE_MMIO_GET(dev) + offs);
116 }
117
uart_rcar_write_8(const struct device * dev,uint32_t offs,uint8_t value)118 static void uart_rcar_write_8(const struct device *dev,
119 uint32_t offs, uint8_t value)
120 {
121 sys_write8(value, DEVICE_MMIO_GET(dev) + offs);
122 }
123
uart_rcar_read_16(const struct device * dev,uint32_t offs)124 static uint16_t uart_rcar_read_16(const struct device *dev,
125 uint32_t offs)
126 {
127 return sys_read16(DEVICE_MMIO_GET(dev) + offs);
128 }
129
uart_rcar_write_16(const struct device * dev,uint32_t offs,uint16_t value)130 static void uart_rcar_write_16(const struct device *dev,
131 uint32_t offs, uint16_t value)
132 {
133 sys_write16(value, DEVICE_MMIO_GET(dev) + offs);
134 }
135
uart_rcar_set_baudrate(const struct device * dev,uint32_t baud_rate)136 static void uart_rcar_set_baudrate(const struct device *dev,
137 uint32_t baud_rate)
138 {
139 struct uart_rcar_data *data = dev->data;
140 const struct uart_rcar_cfg *cfg = dev->config;
141 uint8_t reg_val;
142
143 if (cfg->is_hscif) {
144 reg_val = data->clk_rate / (2 * (HSSRR_SRCYC_DEF_VAL + 1) * baud_rate) - 1;
145 } else {
146 reg_val = ((data->clk_rate + 16 * baud_rate) / (32 * baud_rate) - 1);
147 }
148 uart_rcar_write_8(dev, SCBRR, reg_val);
149 }
150
uart_rcar_poll_in(const struct device * dev,unsigned char * p_char)151 static int uart_rcar_poll_in(const struct device *dev, unsigned char *p_char)
152 {
153 struct uart_rcar_data *data = dev->data;
154 uint16_t reg_val;
155 int ret = 0;
156
157 k_spinlock_key_t key = k_spin_lock(&data->lock);
158
159 /* Receive FIFO empty */
160 if (!((uart_rcar_read_16(dev, SCFSR)) & SCFSR_RDF)) {
161 ret = -1;
162 goto unlock;
163 }
164
165 *p_char = uart_rcar_read_8(dev, SCFRDR);
166
167 reg_val = uart_rcar_read_16(dev, SCFSR);
168 reg_val &= ~SCFSR_RDF;
169 uart_rcar_write_16(dev, SCFSR, reg_val);
170
171 unlock:
172 k_spin_unlock(&data->lock, key);
173
174 return ret;
175 }
176
uart_rcar_poll_out(const struct device * dev,unsigned char out_char)177 static void uart_rcar_poll_out(const struct device *dev, unsigned char out_char)
178 {
179 struct uart_rcar_data *data = dev->data;
180 uint16_t reg_val;
181 k_spinlock_key_t key = k_spin_lock(&data->lock);
182
183 /* Wait for empty space in transmit FIFO */
184 while (!(uart_rcar_read_16(dev, SCFSR) & SCFSR_TDFE)) {
185 }
186
187 uart_rcar_write_8(dev, SCFTDR, out_char);
188
189 reg_val = uart_rcar_read_16(dev, SCFSR);
190 reg_val &= ~(SCFSR_TDFE | SCFSR_TEND);
191 uart_rcar_write_16(dev, SCFSR, reg_val);
192
193 k_spin_unlock(&data->lock, key);
194 }
195
uart_rcar_configure(const struct device * dev,const struct uart_config * cfg)196 static int uart_rcar_configure(const struct device *dev,
197 const struct uart_config *cfg)
198 {
199 struct uart_rcar_data *data = dev->data;
200 const struct uart_rcar_cfg *cfg_drv = dev->config;
201
202 uint16_t reg_val;
203 k_spinlock_key_t key;
204
205 if (cfg->parity != UART_CFG_PARITY_NONE ||
206 cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
207 cfg->data_bits != UART_CFG_DATA_BITS_8 ||
208 cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
209 return -ENOTSUP;
210 }
211
212 key = k_spin_lock(&data->lock);
213
214 /* Disable Transmit and Receive */
215 reg_val = uart_rcar_read_16(dev, SCSCR);
216 reg_val &= ~(SCSCR_TE | SCSCR_RE);
217 uart_rcar_write_16(dev, SCSCR, reg_val);
218
219 /* Emptying Transmit and Receive FIFO */
220 reg_val = uart_rcar_read_16(dev, SCFCR);
221 reg_val |= (SCFCR_TFRST | SCFCR_RFRST);
222 uart_rcar_write_16(dev, SCFCR, reg_val);
223
224 /* Resetting Errors Registers */
225 reg_val = uart_rcar_read_16(dev, SCFSR);
226 reg_val &= ~(SCFSR_ER | SCFSR_DR | SCFSR_BRK | SCFSR_RDF);
227 uart_rcar_write_16(dev, SCFSR, reg_val);
228
229 reg_val = uart_rcar_read_16(dev, SCLSR);
230 reg_val &= ~(SCLSR_TO | SCLSR_ORER);
231 uart_rcar_write_16(dev, SCLSR, reg_val);
232
233 /* Select internal clock */
234 reg_val = uart_rcar_read_16(dev, SCSCR);
235 reg_val &= ~(SCSCR_CKE1 | SCSCR_CKE0);
236 uart_rcar_write_16(dev, SCSCR, reg_val);
237
238 /* Serial Configuration (8N1) & Clock divider selection */
239 reg_val = uart_rcar_read_16(dev, SCSMR);
240 reg_val &= ~(SCSMR_C_A | SCSMR_CHR | SCSMR_PE | SCSMR_O_E | SCSMR_STOP |
241 SCSMR_CKS1 | SCSMR_CKS0);
242 uart_rcar_write_16(dev, SCSMR, reg_val);
243
244 if (cfg_drv->is_hscif) {
245 /* TODO: calculate the optimal sampling and bit rates based on error rate */
246 uart_rcar_write_16(dev, HSSRR, HSSRR_SRE | HSSRR_SRCYC_DEF_VAL);
247 }
248
249 /* Set baudrate */
250 uart_rcar_set_baudrate(dev, cfg->baudrate);
251
252 /* FIFOs data count trigger configuration */
253 reg_val = uart_rcar_read_16(dev, SCFCR);
254 reg_val &= ~(SCFCR_RTRG1 | SCFCR_RTRG0 | SCFCR_TTRG1 | SCFCR_TTRG0 |
255 SCFCR_MCE | SCFCR_TFRST | SCFCR_RFRST);
256 uart_rcar_write_16(dev, SCFCR, reg_val);
257
258 /* Enable Transmit & Receive + disable Interrupts */
259 reg_val = uart_rcar_read_16(dev, SCSCR);
260 reg_val |= (SCSCR_TE | SCSCR_RE);
261 reg_val &= ~(SCSCR_TIE | SCSCR_RIE | SCSCR_TEIE | SCSCR_REIE |
262 SCSCR_TOIE);
263 uart_rcar_write_16(dev, SCSCR, reg_val);
264
265 data->current_config = *cfg;
266
267 k_spin_unlock(&data->lock, key);
268
269 return 0;
270 }
271
272 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
uart_rcar_config_get(const struct device * dev,struct uart_config * cfg)273 static int uart_rcar_config_get(const struct device *dev,
274 struct uart_config *cfg)
275 {
276 struct uart_rcar_data *data = dev->data;
277
278 *cfg = data->current_config;
279
280 return 0;
281 }
282 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
283
uart_rcar_init(const struct device * dev)284 static int uart_rcar_init(const struct device *dev)
285 {
286 const struct uart_rcar_cfg *config = dev->config;
287 struct uart_rcar_data *data = dev->data;
288 int ret;
289
290 /* Configure dt provided device signals when available */
291 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
292 if (ret < 0) {
293 return ret;
294 }
295
296 if (!device_is_ready(config->clock_dev)) {
297 return -ENODEV;
298 }
299
300 ret = clock_control_on(config->clock_dev,
301 (clock_control_subsys_t)&config->mod_clk);
302 if (ret < 0) {
303 return ret;
304 }
305
306 ret = clock_control_get_rate(config->clock_dev,
307 (clock_control_subsys_t)&config->bus_clk,
308 &data->clk_rate);
309 if (ret < 0) {
310 return ret;
311 }
312
313 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
314
315 ret = uart_rcar_configure(dev, &data->current_config);
316 if (ret != 0) {
317 return ret;
318 }
319
320 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
321 config->irq_config_func(dev);
322 #endif
323
324 return 0;
325 }
326
327 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
328
uart_rcar_irq_is_enabled(const struct device * dev,uint32_t irq)329 static bool uart_rcar_irq_is_enabled(const struct device *dev,
330 uint32_t irq)
331 {
332 return !!(uart_rcar_read_16(dev, SCSCR) & irq);
333 }
334
uart_rcar_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)335 static int uart_rcar_fifo_fill(const struct device *dev,
336 const uint8_t *tx_data,
337 int len)
338 {
339 struct uart_rcar_data *data = dev->data;
340 int num_tx = 0;
341 uint16_t reg_val;
342 k_spinlock_key_t key = k_spin_lock(&data->lock);
343
344 while (((len - num_tx) > 0) &&
345 (uart_rcar_read_16(dev, SCFSR) & SCFSR_TDFE)) {
346 /* Send current byte */
347 uart_rcar_write_8(dev, SCFTDR, tx_data[num_tx]);
348
349 reg_val = uart_rcar_read_16(dev, SCFSR);
350 reg_val &= ~(SCFSR_TDFE | SCFSR_TEND);
351 uart_rcar_write_16(dev, SCFSR, reg_val);
352
353 num_tx++;
354 }
355
356 k_spin_unlock(&data->lock, key);
357
358 return num_tx;
359 }
360
uart_rcar_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)361 static int uart_rcar_fifo_read(const struct device *dev, uint8_t *rx_data,
362 const int size)
363 {
364 struct uart_rcar_data *data = dev->data;
365 int num_rx = 0;
366 uint16_t reg_val;
367 k_spinlock_key_t key = k_spin_lock(&data->lock);
368
369 while (((size - num_rx) > 0) &&
370 (uart_rcar_read_16(dev, SCFSR) & SCFSR_RDF)) {
371 /* Receive current byte */
372 rx_data[num_rx++] = uart_rcar_read_8(dev, SCFRDR);
373
374 reg_val = uart_rcar_read_16(dev, SCFSR);
375 reg_val &= ~(SCFSR_RDF);
376 uart_rcar_write_16(dev, SCFSR, reg_val);
377
378 }
379
380 k_spin_unlock(&data->lock, key);
381
382 return num_rx;
383 }
384
uart_rcar_irq_tx_enable(const struct device * dev)385 static void uart_rcar_irq_tx_enable(const struct device *dev)
386 {
387 struct uart_rcar_data *data = dev->data;
388
389 uint16_t reg_val;
390 k_spinlock_key_t key = k_spin_lock(&data->lock);
391
392 reg_val = uart_rcar_read_16(dev, SCSCR);
393 reg_val |= (SCSCR_TIE);
394 uart_rcar_write_16(dev, SCSCR, reg_val);
395
396 k_spin_unlock(&data->lock, key);
397 }
398
uart_rcar_irq_tx_disable(const struct device * dev)399 static void uart_rcar_irq_tx_disable(const struct device *dev)
400 {
401 struct uart_rcar_data *data = dev->data;
402
403 uint16_t reg_val;
404 k_spinlock_key_t key = k_spin_lock(&data->lock);
405
406 reg_val = uart_rcar_read_16(dev, SCSCR);
407 reg_val &= ~(SCSCR_TIE);
408 uart_rcar_write_16(dev, SCSCR, reg_val);
409
410 k_spin_unlock(&data->lock, key);
411 }
412
uart_rcar_irq_tx_ready(const struct device * dev)413 static int uart_rcar_irq_tx_ready(const struct device *dev)
414 {
415 return !!(uart_rcar_read_16(dev, SCFSR) & SCFSR_TDFE);
416 }
417
uart_rcar_irq_rx_enable(const struct device * dev)418 static void uart_rcar_irq_rx_enable(const struct device *dev)
419 {
420 struct uart_rcar_data *data = dev->data;
421
422 uint16_t reg_val;
423 k_spinlock_key_t key = k_spin_lock(&data->lock);
424
425 reg_val = uart_rcar_read_16(dev, SCSCR);
426 reg_val |= (SCSCR_RIE);
427 uart_rcar_write_16(dev, SCSCR, reg_val);
428
429 k_spin_unlock(&data->lock, key);
430 }
431
uart_rcar_irq_rx_disable(const struct device * dev)432 static void uart_rcar_irq_rx_disable(const struct device *dev)
433 {
434 struct uart_rcar_data *data = dev->data;
435
436 uint16_t reg_val;
437 k_spinlock_key_t key = k_spin_lock(&data->lock);
438
439 reg_val = uart_rcar_read_16(dev, SCSCR);
440 reg_val &= ~(SCSCR_RIE);
441 uart_rcar_write_16(dev, SCSCR, reg_val);
442
443 k_spin_unlock(&data->lock, key);
444 }
445
uart_rcar_irq_rx_ready(const struct device * dev)446 static int uart_rcar_irq_rx_ready(const struct device *dev)
447 {
448 return !!(uart_rcar_read_16(dev, SCFSR) & SCFSR_RDF);
449 }
450
uart_rcar_irq_err_enable(const struct device * dev)451 static void uart_rcar_irq_err_enable(const struct device *dev)
452 {
453 struct uart_rcar_data *data = dev->data;
454
455 uint16_t reg_val;
456 k_spinlock_key_t key = k_spin_lock(&data->lock);
457
458 reg_val = uart_rcar_read_16(dev, SCSCR);
459 reg_val |= (SCSCR_REIE);
460 uart_rcar_write_16(dev, SCSCR, reg_val);
461
462 k_spin_unlock(&data->lock, key);
463 }
464
uart_rcar_irq_err_disable(const struct device * dev)465 static void uart_rcar_irq_err_disable(const struct device *dev)
466 {
467 struct uart_rcar_data *data = dev->data;
468
469 uint16_t reg_val;
470 k_spinlock_key_t key = k_spin_lock(&data->lock);
471
472 reg_val = uart_rcar_read_16(dev, SCSCR);
473 reg_val &= ~(SCSCR_REIE);
474 uart_rcar_write_16(dev, SCSCR, reg_val);
475
476 k_spin_unlock(&data->lock, key);
477 }
478
uart_rcar_irq_is_pending(const struct device * dev)479 static int uart_rcar_irq_is_pending(const struct device *dev)
480 {
481 return (uart_rcar_irq_rx_ready(dev) && uart_rcar_irq_is_enabled(dev, SCSCR_RIE)) ||
482 (uart_rcar_irq_tx_ready(dev) && uart_rcar_irq_is_enabled(dev, SCSCR_TIE));
483 }
484
uart_rcar_irq_update(const struct device * dev)485 static int uart_rcar_irq_update(const struct device *dev)
486 {
487 return 1;
488 }
489
uart_rcar_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)490 static void uart_rcar_irq_callback_set(const struct device *dev,
491 uart_irq_callback_user_data_t cb,
492 void *cb_data)
493 {
494 struct uart_rcar_data *data = dev->data;
495
496 data->callback = cb;
497 data->cb_data = cb_data;
498 }
499
500 /**
501 * @brief Interrupt service routine.
502 *
503 * This simply calls the callback function, if one exists.
504 *
505 * @param arg Argument to ISR.
506 */
uart_rcar_isr(const struct device * dev)507 void uart_rcar_isr(const struct device *dev)
508 {
509 struct uart_rcar_data *data = dev->data;
510
511 if (data->callback) {
512 data->callback(dev, data->cb_data);
513 }
514 }
515
516 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
517
518 static const struct uart_driver_api uart_rcar_driver_api = {
519 .poll_in = uart_rcar_poll_in,
520 .poll_out = uart_rcar_poll_out,
521 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
522 .configure = uart_rcar_configure,
523 .config_get = uart_rcar_config_get,
524 #endif
525 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
526 .fifo_fill = uart_rcar_fifo_fill,
527 .fifo_read = uart_rcar_fifo_read,
528 .irq_tx_enable = uart_rcar_irq_tx_enable,
529 .irq_tx_disable = uart_rcar_irq_tx_disable,
530 .irq_tx_ready = uart_rcar_irq_tx_ready,
531 .irq_rx_enable = uart_rcar_irq_rx_enable,
532 .irq_rx_disable = uart_rcar_irq_rx_disable,
533 .irq_rx_ready = uart_rcar_irq_rx_ready,
534 .irq_err_enable = uart_rcar_irq_err_enable,
535 .irq_err_disable = uart_rcar_irq_err_disable,
536 .irq_is_pending = uart_rcar_irq_is_pending,
537 .irq_update = uart_rcar_irq_update,
538 .irq_callback_set = uart_rcar_irq_callback_set,
539 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
540 };
541
542 /* Device Instantiation */
543 #define UART_RCAR_DECLARE_CFG(n, IRQ_FUNC_INIT, compat) \
544 PINCTRL_DT_INST_DEFINE(n); \
545 static const struct uart_rcar_cfg uart_rcar_cfg_##compat##n = { \
546 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
547 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
548 .mod_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
549 .mod_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
550 .bus_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
551 .bus_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
552 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
553 .is_hscif = DT_INST_NODE_HAS_COMPAT(n, renesas_rcar_hscif), \
554 IRQ_FUNC_INIT \
555 }
556
557 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
558 #define UART_RCAR_CONFIG_FUNC(n, compat) \
559 static void irq_config_func_##compat##n(const struct device *dev) \
560 { \
561 IRQ_CONNECT(DT_INST_IRQN(n), \
562 DT_INST_IRQ(n, priority), \
563 uart_rcar_isr, \
564 DEVICE_DT_INST_GET(n), 0); \
565 \
566 irq_enable(DT_INST_IRQN(n)); \
567 }
568 #define UART_RCAR_IRQ_CFG_FUNC_INIT(n, compat) \
569 .irq_config_func = irq_config_func_##compat##n
570 #define UART_RCAR_INIT_CFG(n, compat) \
571 UART_RCAR_DECLARE_CFG(n, UART_RCAR_IRQ_CFG_FUNC_INIT(n, compat), compat)
572 #else
573 #define UART_RCAR_CONFIG_FUNC(n, compat)
574 #define UART_RCAR_IRQ_CFG_FUNC_INIT
575 #define UART_RCAR_INIT_CFG(n, compat) \
576 UART_RCAR_DECLARE_CFG(n, UART_RCAR_IRQ_CFG_FUNC_INIT, compat)
577 #endif
578
579 #define UART_RCAR_INIT(n, compat) \
580 static struct uart_rcar_data uart_rcar_data_##compat##n = { \
581 .current_config = { \
582 .baudrate = DT_INST_PROP(n, current_speed), \
583 .parity = UART_CFG_PARITY_NONE, \
584 .stop_bits = UART_CFG_STOP_BITS_1, \
585 .data_bits = UART_CFG_DATA_BITS_8, \
586 .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
587 }, \
588 }; \
589 \
590 static const struct uart_rcar_cfg uart_rcar_cfg_##compat##n; \
591 \
592 DEVICE_DT_INST_DEFINE(n, \
593 uart_rcar_init, \
594 NULL, \
595 &uart_rcar_data_##compat##n, \
596 &uart_rcar_cfg_##compat##n, \
597 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
598 &uart_rcar_driver_api); \
599 \
600 UART_RCAR_CONFIG_FUNC(n, compat) \
601 \
602 UART_RCAR_INIT_CFG(n, compat);
603
604 DT_INST_FOREACH_STATUS_OKAY_VARGS(UART_RCAR_INIT, DT_DRV_COMPAT)
605
606 #undef DT_DRV_COMPAT
607 #define DT_DRV_COMPAT renesas_rcar_hscif
608
609 DT_INST_FOREACH_STATUS_OKAY_VARGS(UART_RCAR_INIT, DT_DRV_COMPAT)
610
