1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef DMA_IPROC_PAX 8 #define DMA_IPROC_PAX 9 10 /* Broadcom PAX-DMA RM register defines */ 11 #define PAX_DMA_REG_ADDR(_base, _offs) ((_base) + (_offs)) 12 #define PAX_DMA_RING_ADDR_OFFSET(_ring) (0x10000 * (_ring)) 13 14 /* Per-Ring register offsets */ 15 #define RING_VER 0x000 16 #define RING_BD_START_ADDR 0x004 17 #define RING_BD_READ_PTR 0x008 18 #define RING_BD_WRITE_PTR 0x00c 19 #define RING_BD_READ_PTR_DDR_LS 0x010 20 #define RING_BD_READ_PTR_DDR_MS 0x014 21 #define RING_CMPL_START_ADDR 0x018 22 #define RING_CMPL_WRITE_PTR 0x01c 23 #define RING_NUM_REQ_RECV_LS 0x020 24 #define RING_NUM_REQ_RECV_MS 0x024 25 #define RING_NUM_REQ_TRANS_LS 0x028 26 #define RING_NUM_REQ_TRANS_MS 0x02c 27 #define RING_NUM_REQ_OUTSTAND 0x030 28 #define RING_CONTROL 0x034 29 #define RING_FLUSH_DONE 0x038 30 #define RING_MSI_ADDR_LS 0x03c 31 #define RING_MSI_ADDR_MS 0x040 32 #define RING_CMPL_WR_PTR_DDR_CONTROL 0x048 33 #define RING_BD_READ_PTR_DDR_CONTROL 0x04c 34 #define RING_WRITE_SEQ_NUM 0x050 35 #define RING_READ_SEQ_NUM 0x054 36 #define RING_BD_MEM_WRITE_ADDRESS 0x058 37 #define RING_AXI_BEAT_CNT 0x05c 38 #define RING_AXI_BURST_CNT 0x060 39 #define RING_MSI_DATA_VALUE 0x064 40 #define RING_PACKET_ALIGNMENT_STATUS0 0x068 41 #define RING_PACKET_ALIGNMENT_STATUS1 0x06c 42 #define RING_PACKET_ALIGNMENT_STATUS2 0x070 43 #define RING_DOORBELL_BD_WRITE_COUNT 0x074 44 45 /* RING Manager Common Registers */ 46 #define RM_COMM_CTRL_REG(_ring) (0x100 * (_ring)) 47 #define RM_MSI_DEVID_REG(_ring) (0x100 * (_ring) + 0x4) 48 49 #define RM_AE0_AE_CONTROL 0x2000 50 #define RM_AE0_NUMBER_OF_PACKETS_RECEIVED_LS_BITS 0x2004 51 #define RM_AE0_NUMBER_OF_PACKETS_RECEIVED_MS_BITS 0x2008 52 #define RM_AE0_NUMBER_OF_PACKETS_TRANSMITTED_LS_BITS 0x200c 53 #define RM_AE0_NUMBER_OF_PACKETS_TRANSMITTED_MS_BITS 0x2010 54 #define RM_AE0_OUTSTANDING_PACKET 0x2014 55 #define RM_AE0_AE_FLUSH_STATUS 0x2018 56 #define RM_AE0_AE_FIFO_WRITE_POINTER 0x201c 57 #define RM_AE0_AE_FIFO_READ_POINTER 0x2020 58 #define RM_AE1_AE_CONTROL 0x2100 59 #define RM_AE1_NUMBER_OF_PACKETS_RECEIVED_LS_BITS 0x2104 60 #define RM_AE1_NUMBER_OF_PACKETS_RECEIVED_MS_BITS 0x2108 61 #define RM_AE1_NUMBER_OF_PACKETS_TRANSMITTED_LS_BITS 0x210c 62 #define RM_AE1_NUMBER_OF_PACKETS_TRANSMITTED_MS_BITS 0x2110 63 #define RM_AE1_OUTSTANDING_PACKET 0x2114 64 #define RM_AE1_AE_FLUSH_STATUS 0x2118 65 #define RM_AE1_AE_FIFO_WRITE_POINTER 0x211c 66 #define RM_AE1_AE_FIFO_READ_POINTER 0x2120 67 68 #define RM_COMM_RING_SECURITY_SETTING 0x3000 69 #define RM_COMM_CONTROL 0x3008 70 #define RM_COMM_TIMER_CONTROL_0 0x300c 71 #define RM_COMM_TIMER_CONTROL_1 0x3010 72 #define RM_COMM_BD_THRESHOLD 0x3014 73 #define RM_COMM_BURST_LENGTH 0x3018 74 #define RM_COMM_FIFO_FULL_THRESHOLD 0x301c 75 #define RM_COMM_MASK_SEQUENCE_MAX_COUNT 0x3020 76 #define RM_COMM_AE_TIMEOUT 0x3024 77 #define RM_COMM_RING_OR_AE_STATUS_LOG_ENABLE 0x3028 78 #define RM_COMM_RING_FLUSH_TIMEOUT 0x302c 79 #define RM_COMM_MEMORY_CONFIGURATION 0x3030 80 #define RM_COMM_AXI_CONTROL 0x3034 81 #define RM_COMM_GENERAL_MSI_DEVICE_ID 0x3038 82 #define RM_COMM_GENERAL_MSI_ADDRESS_LS 0x303c 83 #define RM_COMM_GENERAL_MSI_ADDRESS_MS 0x3040 84 #define RM_COMM_CONFIG_INTERRUPT_STATUS_MASK 0x3044 85 #define RM_COMM_CONFIG_INTERRUPT_STATUS_CLEAR 0x3048 86 #define RM_COMM_TOGGLE_INTERRUPT_STATUS_MASK 0x304c 87 #define RM_COMM_TOGGLE_INTERRUPT_STATUS_CLEAR 0x3050 88 #define RM_COMM_DDR_ADDR_GEN_INTERRUPT_STATUS_MASK 0x3054 89 #define RM_COMM_DDR_ADDR_GEN_INTERRUPT_STATUS_CLEAR 0x3058 90 #define RM_COMM_PACKET_ALIGNMENT_INTERRUPT_STATUS_MASK 0x305c 91 #define RM_COMM_PACKET_ALIGNMENT_INTERRUPT_STATUS_CLEAR 0x3060 92 #define RM_COMM_AE_INTERFACE_GROUP_0_INTERRUPT_MASK 0x3064 93 #define RM_COMM_AE_INTERFACE_GROUP_0_INTERRUPT_CLEAR 0x3068 94 #define RM_COMM_AE_INTERFACE_GROUP_1_INTERRUPT_MASK 0x306c 95 #define RM_COMM_AE_INTERFACE_GROUP_1_INTERRUPT_CLEAR 0x3070 96 #define RM_COMM_AE_INTERFACE_GROUP_2_INTERRUPT_MASK 0x3074 97 #define RM_COMM_AE_INTERFACE_GROUP_2_INTERRUPT_CLEAR 0x3078 98 #define RM_COMM_AE_INTERFACE_GROUP_3_INTERRUPT_MASK 0x307c 99 #define RM_COMM_AE_INTERFACE_GROUP_3_INTERRUPT_CLEAR 0x3080 100 #define RM_COMM_AE_INTERFACE_GROUP_4_INTERRUPT_MASK 0x3084 101 #define RM_COMM_AE_INTERFACE_GROUP_4_INTERRUPT_CLEAR 0x3088 102 #define RM_COMM_AE_INTERFACE_GROUP_5_INTERRUPT_MASK 0x308c 103 #define RM_COMM_AE_INTERFACE_GROUP_5_INTERRUPT_CLEAR 0x3090 104 #define RM_COMM_AE_INTERFACE_GROUP_6_INTERRUPT_MASK 0x3094 105 #define RM_COMM_AE_INTERFACE_GROUP_6_INTERRUPT_CLEAR 0x3098 106 #define RM_COMM_AE_INTERFACE_GROUP_7_INTERRUPT_MASK 0x309c 107 #define RM_COMM_AE_INTERFACE_GROUP_7_INTERRUPT_CLEAR 0x30a0 108 #define RM_COMM_AE_INTERFACE_TOP_INTERRUPT_STATUS_MASK 0x30a4 109 #define RM_COMM_AE_INTERFACE_TOP_INTERRUPT_STATUS_CLEAR 0x30a8 110 #define RM_COMM_REORDER_INTERRUPT_STATUS_MASK 0x30ac 111 #define RM_COMM_REORDER_INTERRUPT_STATUS_CLEAR 0x30b0 112 #define RM_COMM_DME_INTERRUPT_STATUS_MASK 0x30b4 113 #define RM_COMM_DME_INTERRUPT_STATUS_CLEAR 0x30b8 114 #define RM_COMM_REORDER_FIFO_PROG_THRESHOLD 0x30bc 115 #define RM_COMM_GROUP_PKT_EXTENSION_SUPPORT 0x30c0 116 #define RM_COMM_GENERAL_MSI_DATA_VALUE 0x30c4 117 #define RM_COMM_AXI_READ_BURST_THRESHOLD 0x30c8 118 #define RM_COMM_GROUP_RING_COUNT 0x30cc 119 #define RM_COMM_MSI_DISABLE 0x30d8 120 #define RM_COMM_RESERVE 0x30fc 121 #define RM_COMM_RING_FLUSH_STATUS 0x3100 122 #define RM_COMM_RING_SEQUENCE_NUMBER_OVERFLOW 0x3104 123 #define RM_COMM_AE_SEQUENCE_NUMBER_OVERFLOW 0x3108 124 #define RM_COMM_MAX_SEQUENCE_NUMBER_FOR_ANY_RING 0x310c 125 #define RM_COMM_MAX_SEQUENCE_NUMBER_ON_MONITOR_RING 0x3110 126 #define RM_COMM_MAX_SEQUENCE_NUMBER_ON_ANY_AE 0x3114 127 #define RM_COMM_MAX_SEQUENCE_NUMBER_ON_MONITOR_AE 0x3118 128 #define RM_COMM_MIN_MAX_LATENCY_MONITOR_RING_TOGGLE 0x311c 129 #define RM_COMM_MIN_MAX_LATENCY_MONITOR_RING_ADDRESSGEN 0x3120 130 #define RM_COMM_RING_ACTIVITY 0x3124 131 #define RM_COMM_AE_ACTIVITY 0x3128 132 #define RM_COMM_MAIN_HW_INIT_DONE 0x312c 133 #define RM_COMM_MEMORY_POWER_STATUS 0x3130 134 #define RM_COMM_CONFIG_STATUS_0 0x3134 135 #define RM_COMM_CONFIG_STATUS_1 0x3138 136 #define RM_COMM_TOGGLE_STATUS_0 0x313c 137 #define RM_COMM_TOGGLE_STATUS_1 0x3140 138 #define RM_COMM_DDR_ADDR_GEN_STATUS_0 0x3144 139 #define RM_COMM_DDR_ADDR_GEN_STATUS_1 0x3148 140 #define RM_COMM_PACKET_ALIGNMENT_STATUS_0 0x314c 141 #define RM_COMM_PACKET_ALIGNMENT_STATUS_1 0x3150 142 #define RM_COMM_PACKET_ALIGNMENT_STATUS_2 0x3154 143 #define RM_COMM_PACKET_ALIGNMENT_STATUS_3 0x3158 144 #define RM_COMM_AE_INTERFACE_GROUP_0_STATUS_0 0x315c 145 #define RM_COMM_AE_INTERFACE_GROUP_0_STATUS_1 0x3160 146 #define RM_COMM_AE_INTERFACE_GROUP_1_STATUS_0 0x3164 147 #define RM_COMM_AE_INTERFACE_GROUP_1_STATUS_1 0x3168 148 #define RM_COMM_AE_INTERFACE_GROUP_2_STATUS_0 0x316c 149 #define RM_COMM_AE_INTERFACE_GROUP_2_STATUS_1 0x3170 150 #define RM_COMM_AE_INTERFACE_GROUP_3_STATUS_0 0x3174 151 #define RM_COMM_AE_INTERFACE_GROUP_3_STATUS_1 0x3178 152 #define RM_COMM_AE_INTERFACE_GROUP_4_STATUS_0 0x317c 153 #define RM_COMM_AE_INTERFACE_GROUP_4_STATUS_1 0x3180 154 #define RM_COMM_AE_INTERFACE_GROUP_5_STATUS_0 0x3184 155 #define RM_COMM_AE_INTERFACE_GROUP_5_STATUS_1 0x3188 156 #define RM_COMM_AE_INTERFACE_GROUP_6_STATUS_0 0x318c 157 #define RM_COMM_AE_INTERFACE_GROUP_6_STATUS_1 0x3190 158 #define RM_COMM_AE_INTERFACE_GROUP_7_STATUS_0 0x3194 159 #define RM_COMM_AE_INTERFACE_GROUP_7_STATUS_1 0x3198 160 #define RM_COMM_AE_INTERFACE_TOP_STATUS_0 0x319c 161 #define RM_COMM_AE_INTERFACE_TOP_STATUS_1 0x31a0 162 #define RM_COMM_REORDER_STATUS_0 0x31a4 163 #define RM_COMM_REORDER_STATUS_1 0x31a8 164 #define RM_COMM_REORDER_STATUS_2 0x31ac 165 #define RM_COMM_REORDER_STATUS_3 0x31b0 166 #define RM_COMM_REORDER_STATUS_4 0x31b4 167 #define RM_COMM_REORDER_STATUS_5 0x31b8 168 #define RM_COMM_CONFIG_INTERRUPT_STATUS 0x31bc 169 #define RM_COMM_TOGGLE_INTERRUPT_STATUS 0x31c0 170 #define RM_COMM_DDR_ADDR_GEN_INTERRUPT_STATUS 0x31c4 171 #define RM_COMM_PACKET_ALIGNMENT_INTERRUPT_STATUS 0x31c8 172 #define RM_COMM_AE_INTERFACE_GROUP_0_INTERRUPT_STATUS 0x31cc 173 #define RM_COMM_AE_INTERFACE_GROUP_1_INTERRUPT_STATUS 0x31d0 174 #define RM_COMM_AE_INTERFACE_GROUP_2_INTERRUPT_STATUS 0x31d4 175 #define RM_COMM_AE_INTERFACE_GROUP_3_INTERRUPT_STATUS 0x31d8 176 #define RM_COMM_AE_INTERFACE_GROUP_4_INTERRUPT_STATUS 0x31dc 177 #define RM_COMM_AE_INTERFACE_GROUP_5_INTERRUPT_STATUS 0x31e0 178 #define RM_COMM_AE_INTERFACE_GROUP_6_INTERRUPT_STATUS 0x31e4 179 #define RM_COMM_AE_INTERFACE_GROUP_7_INTERRUPT_STATUS 0x31e8 180 #define RM_COMM_AE_INTERFACE_TOP_INTERRUPT_STATUS 0x31ec 181 #define RM_COMM_REORDER_INTERRUPT_STATUS 0x31f0 182 #define RM_COMM_DME_INTERRUPT_STATUS 0x31f4 183 #define RM_COMM_PACKET_ALIGNMENT_STATUS_4 0x31f8 184 #define RM_COMM_PACKET_ALIGNMENT_STATUS_5 0x31fc 185 #define RM_COMM_PACKET_ALIGNMENT_STATUS_6 0x3200 186 #define RM_COMM_MSI_INTR_INTERRUPT_STATUS 0x3204 187 #define RM_COMM_BD_FETCH_MODE_CONTROL 0x3360 188 189 #define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_SHIFT 16 190 #define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_SHIFT_VAL 32 191 #define RM_COMM_THRESHOLD_CFG_RD_FIFO_MAX_THRESHOLD_MASK 0x1FF 192 193 #define RM_COMM_PKT_ALIGNMENT_BD_FIFO_FULL_THRESHOLD_SHIFT 25 194 #define RM_COMM_PKT_ALIGNMENT_BD_FIFO_FULL_THRESHOLD_VAL 40 195 #define RM_COMM_PKT_ALIGNMENT_BD_FIFO_FULL_THRESHOLD_MASK 0x7F 196 #define RM_COMM_BD_FIFO_FULL_THRESHOLD_VAL 224 197 #define RM_COMM_BD_FIFO_FULL_THRESHOLD_SHIFT 16 198 #define RM_COMM_BD_FIFO_FULL_THRESHOLD_MASK 0x1FF 199 200 /* PAX_DMA_RM_COMM_RM_BURST_LENGTH */ 201 #define RM_COMM_BD_FETCH_CACHE_ALIGNED_DISABLED BIT(28) 202 #define RM_COMM_VALUE_FOR_DDR_ADDR_GEN_SHIFT 16 203 #define RM_COMM_VALUE_FOR_TOGGLE_SHIFT 0 204 #define RM_COMM_VALUE_FOR_DDR_ADDR_GEN_VAL 32 205 #define RM_COMM_VALUE_FOR_TOGGLE_VAL 32 206 207 #define RM_COMM_DISABLE_GRP_BD_FIFO_FLOW_CONTROL_FOR_PKT_ALIGNMENT BIT(1) 208 #define RM_COMM_DISABLE_PKT_ALIGNMENT_BD_FIFO_FLOW_CONTROL BIT(0) 209 210 /* RM version */ 211 #define RING_VER_MAGIC 0x76303031 212 213 /* Register RING_CONTROL fields */ 214 #define RING_CONTROL_MASK_DISABLE_CONTROL 6 215 #define RING_CONTROL_FLUSH BIT(5) 216 #define RING_CONTROL_ACTIVE BIT(4) 217 218 /* Register RING_FLUSH_DONE fields */ 219 #define RING_FLUSH_DONE_MASK 0x1 220 221 #define RING_MASK_SEQ_MAX_COUNT_MASK 0x3ff 222 223 /* RM_COMM_MAIN_HW_INIT_DONE DONE fields */ 224 #define RM_COMM_MAIN_HW_INIT_DONE_MASK 0x1 225 226 /* Register RING_CMPL_WR_PTR_DDR_CONTROL fields */ 227 #define RING_BD_READ_PTR_DDR_TIMER_VAL_SHIFT 16 228 #define RING_BD_READ_PTR_DDR_TIMER_VAL_MASK 0xffff 229 #define RING_BD_READ_PTR_DDR_ENABLE_SHIFT 15 230 #define RING_BD_READ_PTR_DDR_ENABLE_MASK 0x1 231 232 /* Register RING_BD_READ_PTR_DDR_CONTROL fields */ 233 #define RING_BD_CMPL_WR_PTR_DDR_TIMER_VAL_SHIFT 16 234 #define RING_BD_CMPL_WR_PTR_DDR_TIMER_VAL_MASK 0xffff 235 #define RING_BD_CMPL_WR_PTR_DDR_ENABLE_SHIFT 15 236 #define RING_BD_CMPL_WR_PTR_DDR_ENABLE_MASK 0x1 237 238 /* 239 * AE_TIMEOUT is (2^AE_TIMEOUT_BITS) - (2 * NumOfAEs * 2^FIFO_DEPTH_BITS) 240 * AE_TIMEOUT_BITS=32, NumOfAEs=2, FIFO_DEPTH_BITS=5 241 * timeout val = 2^32 - 2*2*2^5 242 */ 243 #define RM_COMM_AE_TIMEOUT_VAL 0xffffff80 244 245 /* RM timer control fields for 4 rings */ 246 #define RM_COMM_TIMER_CONTROL_FAST 0xaf 247 #define RM_COMM_TIMER_CONTROL_FAST_SHIFT 16 248 #define RM_COMM_TIMER_CONTROL_MEDIUM 0x15e 249 #define RM_COMM_TIMER_CONTROL0_VAL \ 250 ((RM_COMM_TIMER_CONTROL_FAST << RM_COMM_TIMER_CONTROL_FAST_SHIFT) | \ 251 (RM_COMM_TIMER_CONTROL_MEDIUM)) 252 #define RM_COMM_TIMER_CONTROL_SLOW 0x2bc 253 #define RM_COMM_TIMER_CONTROL_SLOW_SHIFT 16 254 #define RM_COMM_TIMER_CONTROL_IDLE 0x578 255 #define RM_COMM_TIMER_CONTROL1_VAL \ 256 ((RM_COMM_TIMER_CONTROL_SLOW << RM_COMM_TIMER_CONTROL_SLOW_SHIFT) | \ 257 (RM_COMM_TIMER_CONTROL_IDLE)) 258 #define RM_COMM_RM_BURST_LENGTH 0x80008 259 260 /* Register RM_COMM_AXI_CONTROL fields */ 261 #define RM_COMM_AXI_CONTROL_RD_CH_EN_SHIFT 24 262 #define RM_COMM_AXI_CONTROL_RD_CH_EN \ 263 BIT(RM_COMM_AXI_CONTROL_RD_CH_EN_SHIFT) 264 #define RM_COMM_AXI_CONTROL_WR_CH_EN_SHIFT 28 265 #define RM_COMM_AXI_CONTROL_WR_CH_EN \ 266 BIT(RM_COMM_AXI_CONTROL_WR_CH_EN_SHIFT) 267 268 /* Register Per-ring RING_COMMON_CONTROL fields */ 269 #define RING_COMM_CTRL_AE_GROUP_SHIFT 0 270 #define RING_COMM_CTRL_AE_GROUP_MASK (0x7 << RING_COMM_CTRL_AE_GROUP_SHIFT) 271 272 /* Register AE0_AE_CONTROL/AE1_AE_CONTROL fields */ 273 #define RM_AE_CONTROL_ACTIVE BIT(4) 274 #define RM_AE_CTRL_AE_GROUP_SHIFT 0 275 #define RM_AE_CTRL_AE_GROUP_MASK (0x7 << RM_AE_CTRL_AE_GROUP_SHIFT) 276 277 /* Register RING_CMPL_WR_PTR_DDR_CONTROL fields */ 278 #define RING_DDR_CONTROL_COUNT_SHIFT 0 279 #define RING_DDR_CONTROL_COUNT_MASK 0x3ff 280 #define RING_DDR_CONTROL_COUNT(x) (((x) & RING_DDR_CONTROL_COUNT_MASK) \ 281 << RING_DDR_CONTROL_COUNT_SHIFT) 282 #define RING_DDR_CONTROL_COUNT_VAL 0x1U 283 #define RING_DDR_CONTROL_ENABLE_SHIFT 15 284 #define RING_DDR_CONTROL_ENABLE BIT(RING_DDR_CONTROL_ENABLE_SHIFT) 285 #define RING_DDR_CONTROL_TIMER_SHIFT 16 286 #define RING_DDR_CONTROL_TIMER_MASK 0xffff 287 #define RING_DDR_CONTROL_TIMER(x) (((x) & RING_DDR_CONTROL_TIMER_MASK) \ 288 << RING_DDR_CONTROL_TIMER_SHIFT) 289 290 /* 291 * Set no timeout value for completion write path as it would generate 292 * multiple interrupts during large transfers. And if timeout value is 293 * set, completion write pointers has to be checked on each interrupt 294 * to ensure that transfer is actually done. 295 */ 296 #define RING_DDR_CONTROL_TIMER_VAL (0xFFFF) 297 298 /* completion DME status code */ 299 #define PAX_DMA_STATUS_AXI_RRESP_ERR BIT(0) 300 #define PAX_DMA_STATUS_AXI_BRESP_ERR BIT(1) 301 #define PAX_DMA_STATUS_PCIE_CA_ERR BIT(2) 302 #define PAX_DMA_STATUS_PCIE_UR_ERR BIT(3) 303 #define PAX_DMA_STATUS_PCIE_CMPL_TOUT_ERR BIT(4) 304 #define PAX_DMA_STATUS_PCIE_RX_POISON BIT(5) 305 #define PAX_DMA_STATUS_ERROR_MASK ( \ 306 PAX_DMA_STATUS_AXI_RRESP_ERR | \ 307 PAX_DMA_STATUS_AXI_BRESP_ERR | \ 308 PAX_DMA_STATUS_PCIE_CA_ERR | \ 309 PAX_DMA_STATUS_PCIE_UR_ERR | \ 310 PAX_DMA_STATUS_PCIE_CMPL_TOUT_ERR | \ 311 PAX_DMA_STATUS_PCIE_RX_POISON \ 312 ) 313 /* completion RM status code */ 314 #define RM_COMPLETION_SUCCESS 0x0 315 #define RM_COMPLETION_AE_TIMEOUT 0x3FF 316 317 #define RM_COMM_MSI_CONFIG_INTERRUPT_ACCESS_ERR_MASK BIT(9) 318 #define RM_COMM_MSI_CONFIG_INTERRUPT_BRESP_ERR_MASK BIT(8) 319 #define RM_COMM_MSI_DISABLE_MASK BIT(0) 320 321 /* Buffer Descriptor definitions */ 322 #define PAX_DMA_TYPE_RM_HEADER 0x1 323 #define PAX_DMA_TYPE_NEXT_PTR 0x5 324 325 /* one desc ring size( is 4K, 4K aligned */ 326 #define PAX_DMA_RM_DESC_RING_SIZE 4096 327 #define PAX_DMA_RING_BD_ALIGN_ORDER 12 328 /* completion ring size(bytes) is 8K, 8K aligned */ 329 #define PAX_DMA_RM_CMPL_RING_SIZE 8192 330 #define PAX_DMA_RING_CMPL_ALIGN_ORDER 13 331 332 #define PAX_DMA_RING_BD_ALIGN_CHECK(addr) \ 333 (!((addr) & ((0x1 << RING_BD_ALIGN_ORDER) - 1))) 334 #define RING_CMPL_ALIGN_CHECK(addr) \ 335 (!((addr) & ((0x1 << RING_CMPL_ALIGN_ORDER) - 1))) 336 337 /* RM descriptor width: 8 bytes */ 338 #define PAX_DMA_RM_DESC_BDWIDTH 8 339 /* completion msg desc takes 1 BD */ 340 #define PAX_DMA_CMPL_DESC_SIZE PAX_DMA_RM_DESC_BDWIDTH 341 /* Next table desc takes 1 BD */ 342 #define PAX_DMA_NEXT_TBL_DESC_SIZE PAX_DMA_RM_DESC_BDWIDTH 343 /* Header desc takes 1 BD */ 344 #define PAX_DMA_HEADER_DESC_SIZE PAX_DMA_RM_DESC_BDWIDTH 345 /* Total BDs in ring: 4K/8bytes = 512 BDs */ 346 #define PAX_DMA_RM_RING_BD_COUNT (PAX_DMA_RM_DESC_RING_SIZE / \ 347 PAX_DMA_RM_DESC_BDWIDTH) 348 349 /* Initial RM header is first BD in ring */ 350 #define PAX_DMA_HEADER_INDEX 0 351 #define PAX_DMA_HEADER_ADDR(_ring) (void *)((uintptr_t)(_ring) + \ 352 PAX_DMA_HEADER_INDEX * PAX_DMA_RM_DESC_BDWIDTH) 353 354 /* NEXT TABLE desc offset is last BD in ring */ 355 #define PAX_DMA_NEXT_TBL_INDEX (PAX_DMA_RM_RING_BD_COUNT - 1) 356 #define PAX_DMA_NEXT_TBL_ADDR(_ring) (void *)((uintptr_t)(_ring) + \ 357 PAX_DMA_NEXT_TBL_INDEX * PAX_DMA_RM_DESC_BDWIDTH) 358 359 /* DMA transfers supported from 4 bytes thru 16M, size aligned to 4 bytes */ 360 #define PAX_DMA_MIN_SIZE 4 361 #define PAX_DMA_MAX_SIZE (16 * 1024 * 1024) 362 363 /* Host and Card address need 4-byte alignment */ 364 #define PAX_DMA_ADDR_ALIGN 4 365 366 #define RM_RING_REG(_pd, _r, _write_ptr) \ 367 ((_pd)->ring[_r].ring_base + (_write_ptr)) 368 #define RM_COMM_REG(_pd, _write_ptr) ((_pd)->rm_comm_base + (_write_ptr)) 369 #define PAX_DMA_REG(_pd, _write_ptr) ((_pd)->dma_base + (_write_ptr)) 370 371 #define PAX_DMA_MAX_CMPL_COUNT 1024 372 #define PAX_DMA_LAST_CMPL_IDX (PAX_DMA_MAX_CMPL_COUNT - 1) 373 374 #define PAX_DMA_RING_ALIGN BIT(PAX_DMA_RING_CMPL_ALIGN_ORDER) 375 /* num of completions received, circular buffer */ 376 #define PAX_DMA_GET_CMPL_COUNT(wptr, rptr) (((wptr) >= (rptr)) ? \ 377 ((wptr) - (rptr)) : (PAX_DMA_MAX_CMPL_COUNT - (rptr) + (wptr))) 378 379 /* location of current cmpl pkt, take care of pointer wrap-around */ 380 #define PAX_DMA_CURR_CMPL_IDX(wptr) \ 381 (((wptr) == 0) ? PAX_DMA_LAST_CMPL_IDX : (wptr) - 1) 382 383 /* Timeout (milliseconds) for completion alert in interrupt mode */ 384 #define PAX_DMA_TIMEOUT 10000 385 386 /* TODO: add macro to enable data memory barrier, to ensure writes to memory */ 387 #define dma_mb() 388 389 /* Max polling cycles for completion wait, >= 1 second */ 390 #define PAX_DMA_MAX_POLL_WAIT 1000000 391 /* Max polling cycles for posted write sync >= 1 second */ 392 #define PAX_DMA_MAX_SYNC_WAIT 1000000 393 394 enum ring_idx { 395 PAX_DMA_RING0 = 0, 396 PAX_DMA_RING1, 397 PAX_DMA_RING2, 398 PAX_DMA_RING3, 399 PAX_DMA_RINGS_MAX 400 }; 401 402 /* 403 * DMA direction 404 */ 405 enum pax_dma_dir { 406 CARD_TO_HOST = 0x1, 407 HOST_TO_CARD = 0x2 408 }; 409 410 /* Completion packet */ 411 struct cmpl_pkt { 412 uint64_t opq : 16; /*pkt_id 15:0*/ 413 uint64_t res : 16; /*reserved 16:31*/ 414 uint64_t dma_status : 16; /*PAX DMA status 32:47*/ 415 uint64_t ae_num : 6; /*RM status[47:53] processing AE number */ 416 uint64_t rm_status : 10; /*RM status[54:63] completion/timeout status*/ 417 } __attribute__ ((__packed__)); 418 419 /* Driver internal structures */ 420 421 struct dma_iproc_pax_addr64 { 422 uint32_t addr_lo; 423 uint32_t addr_hi; 424 } __attribute__((__packed__)); 425 426 /* DMA payload for RM internal API */ 427 struct dma_iproc_pax_payload { 428 uint64_t pci_addr; 429 uint64_t axi_addr; 430 uint32_t xfer_sz; 431 enum pax_dma_dir direction; 432 }; 433 434 /* magic to sync completion of posted writes to host */ 435 struct dma_iproc_pax_write_sync_data { 436 /* sglist count, max 254 */ 437 uint32_t total_pkts:9; 438 /* ring-id 0-3 */ 439 uint32_t ring:2; 440 /* opaque-id 0-31 */ 441 uint32_t opaque:5; 442 /* magic pattern */ 443 uint32_t signature:16; 444 }; 445 446 /* BD ring status */ 447 struct dma_iproc_pax_ring_status { 448 /* current desc write_ptret, write pointer */ 449 void *write_ptr; 450 /* current valid toggle */ 451 uint32_t toggle; 452 /* completion queue read offset */ 453 uint32_t cmpl_rd_offs; 454 /* opaque value for current payload */ 455 uint32_t opq; 456 /* posted write sync data */ 457 struct dma_iproc_pax_write_sync_data sync_data; 458 }; 459 460 struct dma_iproc_pax_ring_data { 461 /* ring index */ 462 uint32_t idx; 463 /* Per-Ring register base */ 464 uint32_t ring_base; 465 /* Allocated mem for BD and CMPL */ 466 void *ring_mem; 467 /* Buffer descriptors, 4K aligned */ 468 void *bd; 469 /* Completion descriptors, 8K aligned */ 470 void *cmpl; 471 /* payload struct for internal API */ 472 struct dma_iproc_pax_payload *payload; 473 /* ring current status */ 474 struct dma_iproc_pax_ring_status curr; 475 /* assigned packet id upto 32 values */ 476 uint32_t pkt_id; 477 /* per-ring lock */ 478 struct k_mutex lock; 479 /* alert for the ring */ 480 struct k_sem alert; 481 /* posted write sync src location */ 482 struct dma_iproc_pax_write_sync_data *sync_loc; 483 /* posted write sync pci dst address */ 484 struct dma_iproc_pax_addr64 sync_pci; 485 /* ring status */ 486 int ring_active; 487 /* dma callback and argument */ 488 dma_callback_t dma_callback; 489 void *callback_arg; 490 uint32_t descs_inflight; 491 uint32_t non_hdr_bd_count; 492 uint32_t total_pkt_count; 493 uintptr_t current_hdr; 494 }; 495 496 struct dma_iproc_pax_data { 497 /* PAXB0 PAX DMA registers */ 498 uint32_t dma_base; 499 /* Ring manager common registers */ 500 uint32_t rm_comm_base; 501 /* Num of rings to use in s/w */ 502 int used_rings; 503 /* DMA lock */ 504 struct k_mutex dma_lock; 505 /* Per-Ring data */ 506 struct dma_iproc_pax_ring_data ring[PAX_DMA_RINGS_MAX]; 507 }; 508 509 /* PAX DMA config */ 510 struct dma_iproc_pax_cfg { 511 /* PAXB0 PAX DMA registers */ 512 uint32_t dma_base; 513 /* Per-Ring register base addr */ 514 uint32_t rm_base; 515 /* Ring manager common registers */ 516 uint32_t rm_comm_base; 517 /* Num of rings to be used */ 518 int use_rings; 519 void *bd_memory_base; 520 uint32_t scr_addr_loc; 521 const struct device *pcie_dev; 522 }; 523 524 #endif 525
