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Searched refs:REG_BANK0_OFFSET (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/sensor/tdk/icm42670/
Dicm42670_reg.h18 #define REG_BANK0_OFFSET 0x0000 macro
28 #define REG_MCLK_RDY (REG_BANK0_OFFSET | 0x00)
29 #define REG_DEVICE_CONFIG (REG_BANK0_OFFSET | 0x01)
30 #define REG_SIGNAL_PATH_RESET (REG_BANK0_OFFSET | 0x02)
31 #define REG_DRIVE_CONFIG1 (REG_BANK0_OFFSET | 0x03)
32 #define REG_DRIVE_CONFIG2 (REG_BANK0_OFFSET | 0x04)
33 #define REG_DRIVE_CONFIG3 (REG_BANK0_OFFSET | 0x05)
34 #define REG_INT_CONFIG (REG_BANK0_OFFSET | 0x06)
35 #define REG_TEMP_DATA1 (REG_BANK0_OFFSET | 0x09)
36 #define REG_TEMP_DATA0 (REG_BANK0_OFFSET | 0x0a)
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/Zephyr-Core-3.7.0/drivers/sensor/tdk/icm42688/
Dicm42688_reg.h32 #define REG_BANK0_OFFSET REG_BANK_OFFSET(BIT_BANK0) macro
39 #define REG_DEVICE_CONFIG (REG_BANK0_OFFSET | 0x11)
40 #define REG_DRIVE_CONFIG (REG_BANK0_OFFSET | 0x13)
41 #define REG_INT_CONFIG (REG_BANK0_OFFSET | 0x14)
42 #define REG_FIFO_CONFIG (REG_BANK0_OFFSET | 0x16)
43 #define REG_TEMP_DATA1 (REG_BANK0_OFFSET | 0x1D)
44 #define REG_TEMP_DATA0 (REG_BANK0_OFFSET | 0x1E)
45 #define REG_ACCEL_DATA_X1 (REG_BANK0_OFFSET | 0x1F)
46 #define REG_ACCEL_DATA_X0 (REG_BANK0_OFFSET | 0x20)
47 #define REG_ACCEL_DATA_Y1 (REG_BANK0_OFFSET | 0x21)
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