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Searched refs:PLL0_MUL (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.7.0/soc/atmel/sam/sam4l/
Dsoc.c54 #define PLL0_MUL (192000000 / XTAL_FREQ) macro
210 PLL0_MUL); in clock_init()