1 /*
2 * Copyright (c) 2024 Ilia Kharin
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT cirque_pinnacle
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/gpio.h>
11 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
12 #include <zephyr/drivers/i2c.h>
13 #endif
14 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
15 #include <zephyr/drivers/spi.h>
16 #endif
17 #include <zephyr/init.h>
18 #include <zephyr/input/input.h>
19 #include <zephyr/kernel.h>
20 #include <zephyr/logging/log.h>
21 #include <zephyr/sys/util.h>
22
23 LOG_MODULE_REGISTER(pinnacle, CONFIG_INPUT_LOG_LEVEL);
24
25 /*
26 * Register Access Protocol Standard Registers.
27 * Standard registers have 5-bit addresses, BIT[4:0], that range from
28 * 0x00 to 0x1F. For reading, a register address has to be combined with
29 * 0xA0 for reading and 0x80 for writing bits, BIT[7:5].
30 */
31 #define PINNACLE_REG_FIRMWARE_ID 0x00 /* R */
32 #define PINNACLE_REG_FIRMWARE_VERSION 0x01 /* R */
33 #define PINNACLE_REG_STATUS1 0x02 /* R/W */
34 #define PINNACLE_REG_SYS_CONFIG1 0x03 /* R/W */
35 #define PINNACLE_REG_FEED_CONFIG1 0x04 /* R/W */
36 #define PINNACLE_REG_FEED_CONFIG2 0x05 /* R/W */
37 #define PINNACLE_REG_FEED_CONFIG3 0x06 /* R/W */
38 #define PINNACLE_REG_CAL_CONFIG1 0x07 /* R/W */
39 #define PINNACLE_REG_PS2_AUX_CONTROL 0x08 /* R/W */
40 #define PINNACLE_REG_SAMPLE_RATE 0x09 /* R/W */
41 #define PINNACLE_REG_Z_IDLE 0x0A /* R/W */
42 #define PINNACLE_REG_Z_SCALER 0x0B /* R/W */
43 #define PINNACLE_REG_SLEEP_INTERVAL 0x0C /* R/W */
44 #define PINNACLE_REG_SLEEP_TIMER 0x0D /* R/W */
45 #define PINNACLE_REG_EMI_THRESHOLD 0x0E /* R/W */
46 #define PINNACLE_REG_PACKET_BYTE0 0x12 /* R */
47 #define PINNACLE_REG_PACKET_BYTE1 0x13 /* R */
48 #define PINNACLE_REG_PACKET_BYTE2 0x14 /* R */
49 #define PINNACLE_REG_PACKET_BYTE3 0x15 /* R */
50 #define PINNACLE_REG_PACKET_BYTE4 0x16 /* R */
51 #define PINNACLE_REG_PACKET_BYTE5 0x17 /* R */
52 #define PINNACLE_REG_GPIO_A_CTRL 0x18 /* R/W */
53 #define PINNACLE_REG_GPIO_A_DATA 0x19 /* R/W */
54 #define PINNACLE_REG_GPIO_B_CTRL_DATA 0x1A /* R/W */
55 /* Value of the extended register */
56 #define PINNACLE_REG_ERA_VALUE 0x1B /* R/W */
57 /* High byte BIT[15:8] of the 16 bit extended register */
58 #define PINNACLE_REG_ERA_ADDR_HIGH 0x1C /* R/W */
59 /* Low byte BIT[7:0] of the 16 bit extended register */
60 #define PINNACLE_REG_ERA_ADDR_LOW 0x1D /* R/W */
61 #define PINNACLE_REG_ERA_CTRL 0x1E /* R/W */
62 #define PINNACLE_REG_PRODUCT_ID 0x1F /* R */
63
64 /* Extended Register Access */
65 #define PINNACLE_ERA_REG_CONFIG 0x0187 /* R/W */
66
67 /* Firmware ASIC ID value */
68 #define PINNACLE_FIRMWARE_ID 0x07
69
70 /* Status1 definition */
71 #define PINNACLE_STATUS1_SW_DR BIT(2)
72 #define PINNACLE_STATUS1_SW_CC BIT(3)
73
74 /* SysConfig1 definition */
75 #define PINNACLE_SYS_CONFIG1_RESET BIT(0)
76 #define PINNACLE_SYS_CONFIG1_SHUTDOWN BIT(1)
77 #define PINNACLE_SYS_CONFIG1_LOW_POWER_MODE BIT(2)
78
79 /* FeedConfig1 definition */
80 #define PINNACLE_FEED_CONFIG1_FEED_ENABLE BIT(0)
81 #define PINNACLE_FEED_CONFIG1_DATA_MODE_ABSOLUTE BIT(1)
82 #define PINNACLE_FEED_CONFIG1_FILTER_DISABLE BIT(2)
83 #define PINNACLE_FEED_CONFIG1_X_DISABLE BIT(3)
84 #define PINNACLE_FEED_CONFIG1_Y_DISABLE BIT(4)
85 #define PINNACLE_FEED_CONFIG1_X_INVERT BIT(6)
86 #define PINNACLE_FEED_CONFIG1_Y_INVERT BIT(7)
87 /* X max to 0 */
88 #define PINNACLE_FEED_CONFIG1_X_DATA_INVERT BIT(6)
89 /* Y max to 0 */
90 #define PINNACLE_FEED_CONFIG1_Y_DATA_INVERT BIT(7)
91
92 /* FeedConfig2 definition */
93 #define PINNACLE_FEED_CONFIG2_INTELLIMOUSE_ENABLE BIT(0)
94 #define PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE BIT(1)
95 #define PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE BIT(2)
96 #define PINNACLE_FEED_CONFIG2_SCROLL_DISABLE BIT(3)
97 #define PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE BIT(4)
98 /* 90 degrees rotation */
99 #define PINNACLE_FEED_CONFIG2_SWAP_X_AND_Y BIT(7)
100
101 /* Relative position status in PacketByte0 */
102 #define PINNACLE_PACKET_BYTE0_BTN_PRIMARY BIT(0)
103 #define PINNACLE_PACKET_BYTE0_BTN_SECONDRY BIT(1)
104
105 /* Extended Register Access Control */
106 #define PINNACLE_ERA_CTRL_READ BIT(0)
107 #define PINNACLE_ERA_CTRL_WRITE BIT(1)
108 #define PINNACLE_ERA_CTRL_READ_AUTO_INC BIT(2)
109 #define PINNACLE_ERA_CTRL_WRITE_AUTO_INC BIT(3)
110 /* Asserting both BIT(1) and BIT(0) means WRITE/Verify */
111 #define PINNACLE_ERA_CTRL_WRITE_VERIFY (BIT(1) | BIT(0))
112 #define PINNACLE_ERA_CTRL_COMPLETE 0x00
113
114 /* Extended Register Access Config */
115 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1 0x00
116 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2 0x40
117 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3 0x80
118 #define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4 0xC0
119
120 /*
121 * Delay and retry count for waiting completion of calibration with 200 ms of
122 * timeout.
123 */
124 #define PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US 50000
125 #define PINNACLE_CALIBRATION_AWAIT_RETRY_COUNT 4
126
127 /*
128 * Delay and retry count for waiting completion of ERA command with 50 ms of
129 * timeout.
130 */
131 #define PINNACLE_ERA_AWAIT_DELAY_POLL_US 10000
132 #define PINNACLE_ERA_AWAIT_RETRY_COUNT 5
133
134 /* Special definitions */
135 #define PINNACLE_SPI_FB 0xFB /* Filler byte */
136 #define PINNACLE_SPI_FC 0xFC /* Auto-increment byte */
137
138 /* Read and write masks */
139 #define PINNACLE_READ_MSK 0xA0
140 #define PINNACLE_WRITE_MSK 0x80
141
142 /* Read and write register addresses */
143 #define PINNACLE_READ_REG(addr) (PINNACLE_READ_MSK | addr)
144 #define PINNACLE_WRITE_REG(addr) (PINNACLE_WRITE_MSK | addr)
145
146 struct pinnacle_bus {
147 union {
148 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
149 struct i2c_dt_spec i2c;
150 #endif
151 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
152 struct spi_dt_spec spi;
153 #endif
154 };
155 bool (*is_ready)(const struct pinnacle_bus *bus);
156 int (*write)(const struct pinnacle_bus *bus, uint8_t address, uint8_t value);
157 int (*seq_write)(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
158 uint8_t count);
159 int (*read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value);
160 int (*seq_read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *data,
161 uint8_t count);
162 };
163
164 enum pinnacle_sensitivity {
165 PINNACLE_SENSITIVITY_X1,
166 PINNACLE_SENSITIVITY_X2,
167 PINNACLE_SENSITIVITY_X3,
168 PINNACLE_SENSITIVITY_X4,
169 };
170
171 struct pinnacle_config {
172 const struct pinnacle_bus bus;
173 struct gpio_dt_spec dr_gpio;
174
175 enum pinnacle_sensitivity sensitivity;
176 bool relative_mode;
177 uint8_t idle_packets_count;
178
179 bool clipping_enabled;
180 bool scaling_enabled;
181 bool invert_x;
182 bool invert_y;
183 bool primary_tap_enabled;
184 bool swap_xy;
185
186 uint16_t active_range_x_min;
187 uint16_t active_range_x_max;
188 uint16_t active_range_y_min;
189 uint16_t active_range_y_max;
190
191 uint16_t resolution_x;
192 uint16_t resolution_y;
193 };
194
195 union pinnacle_sample {
196 struct {
197 uint16_t abs_x;
198 uint16_t abs_y;
199 uint8_t abs_z;
200 };
201 struct {
202 int16_t rel_x;
203 int16_t rel_y;
204 bool btn_primary;
205 };
206 };
207
208 struct pinnacle_data {
209 union pinnacle_sample sample;
210 const struct device *dev;
211 struct gpio_callback dr_cb_data;
212 struct k_work work;
213 };
214
pinnacle_bus_is_ready(const struct device * dev)215 static inline bool pinnacle_bus_is_ready(const struct device *dev)
216 {
217 const struct pinnacle_config *config = dev->config;
218
219 return config->bus.is_ready(&config->bus);
220 }
221
pinnacle_write(const struct device * dev,uint8_t address,uint8_t value)222 static inline int pinnacle_write(const struct device *dev, uint8_t address, uint8_t value)
223 {
224 const struct pinnacle_config *config = dev->config;
225
226 return config->bus.write(&config->bus, address, value);
227 }
pinnacle_seq_write(const struct device * dev,uint8_t * address,uint8_t * value,uint8_t count)228 static inline int pinnacle_seq_write(const struct device *dev, uint8_t *address, uint8_t *value,
229 uint8_t count)
230 {
231 const struct pinnacle_config *config = dev->config;
232
233 return config->bus.seq_write(&config->bus, address, value, count);
234 }
pinnacle_read(const struct device * dev,uint8_t address,uint8_t * value)235 static inline int pinnacle_read(const struct device *dev, uint8_t address, uint8_t *value)
236 {
237 const struct pinnacle_config *config = dev->config;
238
239 return config->bus.read(&config->bus, address, value);
240 }
241
pinnacle_seq_read(const struct device * dev,uint8_t address,uint8_t * data,uint8_t count)242 static inline int pinnacle_seq_read(const struct device *dev, uint8_t address, uint8_t *data,
243 uint8_t count)
244 {
245 const struct pinnacle_config *config = dev->config;
246
247 return config->bus.seq_read(&config->bus, address, data, count);
248 }
249
pinnacle_clear_cmd_complete(const struct device * dev)250 static inline int pinnacle_clear_cmd_complete(const struct device *dev)
251 {
252 const struct pinnacle_config *config = dev->config;
253
254 return config->bus.write(&config->bus, PINNACLE_REG_STATUS1, 0x00);
255 }
256
pinnacle_era_wait_for_completion(const struct device * dev)257 static int pinnacle_era_wait_for_completion(const struct device *dev)
258 {
259 bool ret;
260 uint8_t value;
261
262 ret = WAIT_FOR(pinnacle_read(dev, PINNACLE_REG_ERA_CTRL, &value) == 0 &&
263 value == PINNACLE_ERA_CTRL_COMPLETE,
264 PINNACLE_ERA_AWAIT_RETRY_COUNT * PINNACLE_ERA_AWAIT_DELAY_POLL_US,
265 k_sleep(K_USEC(PINNACLE_ERA_AWAIT_DELAY_POLL_US)));
266 if (!ret) {
267 return -EIO;
268 }
269
270 return 0;
271 }
272
pinnacle_era_write(const struct device * dev,uint16_t address,uint8_t value)273 static int pinnacle_era_write(const struct device *dev, uint16_t address, uint8_t value)
274 {
275 uint8_t address_buf[] = {
276 PINNACLE_REG_ERA_VALUE,
277 PINNACLE_REG_ERA_ADDR_HIGH,
278 PINNACLE_REG_ERA_ADDR_LOW,
279 PINNACLE_REG_ERA_CTRL,
280 };
281 uint8_t value_buf[] = {
282 value,
283 address >> 8,
284 address & 0xFF,
285 PINNACLE_ERA_CTRL_WRITE,
286 };
287 int rc;
288
289 rc = pinnacle_seq_write(dev, address_buf, value_buf, sizeof(address_buf));
290 if (rc) {
291 return rc;
292 }
293
294 return pinnacle_era_wait_for_completion(dev);
295 }
296
pinnacle_era_read(const struct device * dev,uint16_t address,uint8_t * value)297 static int pinnacle_era_read(const struct device *dev, uint16_t address, uint8_t *value)
298 {
299 uint8_t address_buf[] = {
300 PINNACLE_REG_ERA_ADDR_HIGH,
301 PINNACLE_REG_ERA_ADDR_LOW,
302 PINNACLE_REG_ERA_CTRL,
303 };
304 uint8_t value_buf[] = {
305 address >> 8,
306 address & 0xFF,
307 PINNACLE_ERA_CTRL_READ,
308 };
309 int rc;
310
311 rc = pinnacle_seq_write(dev, address_buf, value_buf, sizeof(address_buf));
312 if (rc) {
313 return rc;
314 }
315
316 rc = pinnacle_era_wait_for_completion(dev);
317 if (rc) {
318 return rc;
319 }
320
321 return pinnacle_read(dev, PINNACLE_REG_ERA_VALUE, value);
322 }
323
pinnacle_set_sensitivity(const struct device * dev)324 static int pinnacle_set_sensitivity(const struct device *dev)
325 {
326 const struct pinnacle_config *config = dev->config;
327
328 uint8_t value;
329 int rc;
330
331 rc = pinnacle_era_read(dev, PINNACLE_ERA_REG_CONFIG, &value);
332 if (rc) {
333 return rc;
334 }
335
336 /* Clear BIT(7) and BIT(6) */
337 value &= 0x3F;
338
339 switch (config->sensitivity) {
340 case PINNACLE_SENSITIVITY_X1:
341 value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1;
342 break;
343 case PINNACLE_SENSITIVITY_X2:
344 value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2;
345 break;
346 case PINNACLE_SENSITIVITY_X3:
347 value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3;
348 break;
349 case PINNACLE_SENSITIVITY_X4:
350 value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4;
351 break;
352 }
353
354 rc = pinnacle_era_write(dev, PINNACLE_ERA_REG_CONFIG, value);
355 if (rc) {
356 return rc;
357 }
358
359 /* Clear SW_CC after setting sensitivity */
360 rc = pinnacle_clear_cmd_complete(dev);
361 if (rc) {
362 return rc;
363 }
364
365 return 0;
366 }
367
368 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
pinnacle_is_ready_i2c(const struct pinnacle_bus * bus)369 static bool pinnacle_is_ready_i2c(const struct pinnacle_bus *bus)
370 {
371 if (!i2c_is_ready_dt(&bus->i2c)) {
372 LOG_ERR("I2C bus %s is not ready", bus->i2c.bus->name);
373 return false;
374 }
375
376 return true;
377 }
378
pinnacle_write_i2c(const struct pinnacle_bus * bus,uint8_t address,uint8_t value)379 static int pinnacle_write_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t value)
380 {
381 uint8_t buf[] = {PINNACLE_WRITE_REG(address), value};
382
383 return i2c_write_dt(&bus->i2c, buf, 2);
384 }
385
pinnacle_seq_write_i2c(const struct pinnacle_bus * bus,uint8_t * address,uint8_t * value,uint8_t count)386 static int pinnacle_seq_write_i2c(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
387 uint8_t count)
388 {
389 uint8_t buf[count * 2];
390
391 for (uint8_t i = 0; i < count; ++i) {
392 buf[i * 2] = PINNACLE_WRITE_REG(address[i]);
393 buf[i * 2 + 1] = value[i];
394 }
395
396 return i2c_write_dt(&bus->i2c, buf, count * 2);
397 }
398
pinnacle_read_i2c(const struct pinnacle_bus * bus,uint8_t address,uint8_t * value)399 static int pinnacle_read_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value)
400 {
401 uint8_t reg = PINNACLE_READ_REG(address);
402
403 return i2c_write_read_dt(&bus->i2c, ®, 1, value, 1);
404 }
405
pinnacle_seq_read_i2c(const struct pinnacle_bus * bus,uint8_t address,uint8_t * buf,uint8_t count)406 static int pinnacle_seq_read_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t *buf,
407 uint8_t count)
408 {
409 uint8_t reg = PINNACLE_READ_REG(address);
410
411 return i2c_burst_read_dt(&bus->i2c, reg, buf, count);
412 }
413 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
414
415 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
pinnacle_is_ready_spi(const struct pinnacle_bus * bus)416 static bool pinnacle_is_ready_spi(const struct pinnacle_bus *bus)
417 {
418 if (!spi_is_ready_dt(&bus->spi)) {
419 LOG_ERR("SPI bus %s is not ready", bus->spi.bus->name);
420 return false;
421 }
422
423 return true;
424 }
425
pinnacle_write_spi(const struct pinnacle_bus * bus,uint8_t address,uint8_t value)426 static int pinnacle_write_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t value)
427 {
428 uint8_t tx_data[] = {
429 PINNACLE_WRITE_REG(address),
430 value,
431 };
432 const struct spi_buf tx_buf[] = {{
433 .buf = tx_data,
434 .len = sizeof(tx_data),
435 }};
436 const struct spi_buf_set tx_set = {
437 .buffers = tx_buf,
438 .count = ARRAY_SIZE(tx_buf),
439 };
440
441 return spi_write_dt(&bus->spi, &tx_set);
442 }
443
pinnacle_seq_write_spi(const struct pinnacle_bus * bus,uint8_t * address,uint8_t * value,uint8_t count)444 static int pinnacle_seq_write_spi(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
445 uint8_t count)
446 {
447 uint8_t tx_data[count * 2];
448 const struct spi_buf tx_buf[] = {{
449 .buf = tx_data,
450 .len = sizeof(tx_data),
451 }};
452 const struct spi_buf_set tx_set = {
453 .buffers = tx_buf,
454 .count = ARRAY_SIZE(tx_buf),
455 };
456
457 for (uint8_t i = 0; i < count; ++i) {
458 tx_data[i * 2] = PINNACLE_WRITE_REG(address[i]);
459 tx_data[i * 2 + 1] = value[i];
460 }
461
462 return spi_write_dt(&bus->spi, &tx_set);
463 }
464
pinnacle_read_spi(const struct pinnacle_bus * bus,uint8_t address,uint8_t * value)465 static int pinnacle_read_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value)
466 {
467 uint8_t tx_data[] = {
468 PINNACLE_READ_REG(address),
469 PINNACLE_SPI_FB,
470 PINNACLE_SPI_FB,
471 PINNACLE_SPI_FB,
472 };
473 const struct spi_buf tx_buf[] = {{
474 .buf = tx_data,
475 .len = sizeof(tx_data),
476 }};
477 const struct spi_buf_set tx_set = {
478 .buffers = tx_buf,
479 .count = ARRAY_SIZE(tx_buf),
480 };
481
482 const struct spi_buf rx_buf[] = {
483 {
484 .buf = NULL,
485 .len = 3,
486 },
487 {
488 .buf = value,
489 .len = 1,
490 },
491 };
492 const struct spi_buf_set rx_set = {
493 .buffers = rx_buf,
494 .count = ARRAY_SIZE(rx_buf),
495 };
496
497 int rc;
498
499 rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set);
500 if (rc) {
501 LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name);
502 return rc;
503 }
504
505 return 0;
506 }
507
pinnacle_seq_read_spi(const struct pinnacle_bus * bus,uint8_t address,uint8_t * buf,uint8_t count)508 static int pinnacle_seq_read_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t *buf,
509 uint8_t count)
510 {
511
512 uint8_t size = count + 3;
513 uint8_t tx_data[size];
514
515 tx_data[0] = PINNACLE_READ_REG(address);
516 tx_data[1] = PINNACLE_SPI_FC;
517 tx_data[2] = PINNACLE_SPI_FC;
518
519 uint8_t i = 3;
520
521 for (; i < (count + 2); ++i) {
522 tx_data[i] = PINNACLE_SPI_FC;
523 }
524
525 tx_data[i++] = PINNACLE_SPI_FB;
526
527 const struct spi_buf tx_buf[] = {{
528 .buf = tx_data,
529 .len = size,
530 }};
531 const struct spi_buf_set tx_set = {
532 .buffers = tx_buf,
533 .count = 1,
534 };
535
536 const struct spi_buf rx_buf[] = {
537 {
538 .buf = NULL,
539 .len = 3,
540 },
541 {
542 .buf = buf,
543 .len = count,
544 },
545 };
546 const struct spi_buf_set rx_set = {
547 .buffers = rx_buf,
548 .count = ARRAY_SIZE(rx_buf),
549 };
550
551 int rc;
552
553 rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set);
554 if (rc) {
555 LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name);
556 return rc;
557 }
558
559 return 0;
560 }
561 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
562
pinnacle_decode_sample(const struct device * dev,uint8_t * rx,union pinnacle_sample * sample)563 static void pinnacle_decode_sample(const struct device *dev, uint8_t *rx,
564 union pinnacle_sample *sample)
565 {
566 const struct pinnacle_config *config = dev->config;
567
568 if (config->relative_mode) {
569 if (config->primary_tap_enabled) {
570 sample->btn_primary = (rx[0] & BIT(0)) == BIT(0);
571 }
572 sample->rel_x = ((rx[0] & BIT(4)) == BIT(4)) ? -(256 - rx[1]) : rx[1];
573 sample->rel_y = ((rx[0] & BIT(5)) == BIT(5)) ? -(256 - rx[2]) : rx[2];
574 } else {
575 sample->abs_x = ((rx[2] & 0x0F) << 8) | rx[0];
576 sample->abs_y = ((rx[2] & 0xF0) << 4) | rx[1];
577 sample->abs_z = rx[3] & 0x3F;
578 }
579 }
580
pinnacle_is_idle_sample(const union pinnacle_sample * sample)581 static bool pinnacle_is_idle_sample(const union pinnacle_sample *sample)
582 {
583 return (sample->abs_x == 0 && sample->abs_y == 0 && sample->abs_z == 0);
584 }
585
pinnacle_clip_sample(const struct device * dev,union pinnacle_sample * sample)586 static void pinnacle_clip_sample(const struct device *dev, union pinnacle_sample *sample)
587 {
588 const struct pinnacle_config *config = dev->config;
589
590 if (sample->abs_x < config->active_range_x_min) {
591 sample->abs_x = config->active_range_x_min;
592 }
593 if (sample->abs_x > config->active_range_x_max) {
594 sample->abs_x = config->active_range_x_max;
595 }
596 if (sample->abs_y < config->active_range_y_min) {
597 sample->abs_y = config->active_range_y_min;
598 }
599 if (sample->abs_y > config->active_range_y_max) {
600 sample->abs_y = config->active_range_y_max;
601 }
602 }
603
pinnacle_scale_sample(const struct device * dev,union pinnacle_sample * sample)604 static void pinnacle_scale_sample(const struct device *dev, union pinnacle_sample *sample)
605 {
606 const struct pinnacle_config *config = dev->config;
607
608 uint16_t range_x = config->active_range_x_max - config->active_range_x_min;
609 uint16_t range_y = config->active_range_y_max - config->active_range_y_min;
610
611 sample->abs_x = (uint16_t)((uint32_t)(sample->abs_x - config->active_range_x_min) *
612 config->resolution_x / range_x);
613 sample->abs_y = (uint16_t)((uint32_t)(sample->abs_y - config->active_range_y_min) *
614 config->resolution_y / range_y);
615 }
616
pinnacle_sample_fetch(const struct device * dev,union pinnacle_sample * sample)617 static int pinnacle_sample_fetch(const struct device *dev, union pinnacle_sample *sample)
618 {
619 const struct pinnacle_config *config = dev->config;
620
621 uint8_t rx[4];
622 int rc;
623
624 if (config->relative_mode) {
625 rc = pinnacle_seq_read(dev, PINNACLE_REG_PACKET_BYTE0, rx, 3);
626 } else {
627 rc = pinnacle_seq_read(dev, PINNACLE_REG_PACKET_BYTE2, rx, 4);
628 }
629
630 if (rc) {
631 LOG_ERR("Failed to read data from SPI device");
632 return rc;
633 }
634
635 pinnacle_decode_sample(dev, rx, sample);
636
637 rc = pinnacle_write(dev, PINNACLE_REG_STATUS1, 0x00);
638 if (rc) {
639 LOG_ERR("Failed to clear SW_CC and SW_DR");
640 return rc;
641 }
642
643 return 0;
644 }
645
pinnacle_handle_interrupt(const struct device * dev)646 static int pinnacle_handle_interrupt(const struct device *dev)
647 {
648 const struct pinnacle_config *config = dev->config;
649 struct pinnacle_data *drv_data = dev->data;
650 union pinnacle_sample *sample = &drv_data->sample;
651
652 int rc;
653
654 rc = pinnacle_sample_fetch(dev, sample);
655 if (rc) {
656 LOG_ERR("Failed to read data packets");
657 return rc;
658 }
659
660 if (config->relative_mode) {
661 input_report_rel(dev, INPUT_REL_X, sample->rel_x, false, K_FOREVER);
662 input_report_rel(dev, INPUT_REL_Y, sample->rel_y, !config->primary_tap_enabled,
663 K_FOREVER);
664 if (config->primary_tap_enabled) {
665 input_report_key(dev, INPUT_BTN_TOUCH, sample->btn_primary, true,
666 K_FOREVER);
667 }
668 } else {
669 if (config->clipping_enabled && !pinnacle_is_idle_sample(sample)) {
670 pinnacle_clip_sample(dev, sample);
671 if (config->scaling_enabled) {
672 pinnacle_scale_sample(dev, sample);
673 }
674 }
675
676 input_report_abs(dev, INPUT_ABS_X, sample->abs_x, false, K_FOREVER);
677 input_report_abs(dev, INPUT_ABS_Y, sample->abs_y, false, K_FOREVER);
678 input_report_abs(dev, INPUT_ABS_Z, sample->abs_z, true, K_FOREVER);
679 }
680
681 return 0;
682 }
683
pinnacle_data_ready_gpio_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)684 static void pinnacle_data_ready_gpio_callback(const struct device *dev, struct gpio_callback *cb,
685 uint32_t pins)
686 {
687 struct pinnacle_data *drv_data = CONTAINER_OF(cb, struct pinnacle_data, dr_cb_data);
688
689 k_work_submit(&drv_data->work);
690 }
691
pinnacle_work_cb(struct k_work * work)692 static void pinnacle_work_cb(struct k_work *work)
693 {
694 struct pinnacle_data *drv_data = CONTAINER_OF(work, struct pinnacle_data, work);
695
696 pinnacle_handle_interrupt(drv_data->dev);
697 }
698
pinnacle_init_interrupt(const struct device * dev)699 int pinnacle_init_interrupt(const struct device *dev)
700 {
701 struct pinnacle_data *drv_data = dev->data;
702 const struct pinnacle_config *config = dev->config;
703 const struct gpio_dt_spec *gpio = &config->dr_gpio;
704
705 int rc;
706
707 drv_data->dev = dev;
708 drv_data->work.handler = pinnacle_work_cb;
709
710 /* Configure GPIO pin for HW_DR signal */
711 rc = gpio_is_ready_dt(gpio);
712 if (!rc) {
713 LOG_ERR("GPIO device %s/%d is not ready", gpio->port->name, gpio->pin);
714 return -ENODEV;
715 }
716
717 rc = gpio_pin_configure_dt(gpio, GPIO_INPUT);
718 if (rc) {
719 LOG_ERR("Failed to configure %s/%d as input", gpio->port->name, gpio->pin);
720 return rc;
721 }
722
723 rc = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_TO_ACTIVE);
724 if (rc) {
725 LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin);
726 return rc;
727 }
728
729 gpio_init_callback(&drv_data->dr_cb_data, pinnacle_data_ready_gpio_callback,
730 BIT(gpio->pin));
731
732 rc = gpio_add_callback(gpio->port, &drv_data->dr_cb_data);
733 if (rc) {
734 LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin);
735 return rc;
736 }
737
738 return 0;
739 }
740
pinnacle_init(const struct device * dev)741 static int pinnacle_init(const struct device *dev)
742 {
743 const struct pinnacle_config *config = dev->config;
744
745 int rc;
746 bool ret;
747 uint8_t value;
748
749 if (!pinnacle_bus_is_ready(dev)) {
750 return -ENODEV;
751 }
752
753 rc = pinnacle_read(dev, PINNACLE_REG_FIRMWARE_ID, &value);
754 if (rc) {
755 LOG_ERR("Failed to read FirmwareId");
756 return rc;
757 }
758
759 if (value != PINNACLE_FIRMWARE_ID) {
760 LOG_ERR("Incorrect Firmware ASIC ID %x", value);
761 return -ENODEV;
762 }
763
764 /* Wait until the calibration is completed (SW_CC is asserted) */
765 ret = WAIT_FOR(pinnacle_read(dev, PINNACLE_REG_STATUS1, &value) == 0 &&
766 (value & PINNACLE_STATUS1_SW_CC) == PINNACLE_STATUS1_SW_CC,
767 PINNACLE_CALIBRATION_AWAIT_RETRY_COUNT *
768 PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US,
769 k_sleep(K_USEC(PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US)));
770 if (!ret) {
771 LOG_ERR("Failed to wait for calibration complition");
772 return -EIO;
773 }
774
775 /* Clear SW_CC after Power on Reset */
776 rc = pinnacle_clear_cmd_complete(dev);
777 if (rc) {
778 LOG_ERR("Failed to clear SW_CC in Status1");
779 return -EIO;
780 }
781
782 /* Set trackpad sensitivity */
783 rc = pinnacle_set_sensitivity(dev);
784 if (rc) {
785 LOG_ERR("Failed to set sensitivity");
786 return -EIO;
787 }
788
789 rc = pinnacle_write(dev, PINNACLE_REG_SYS_CONFIG1, 0x00);
790 if (rc) {
791 LOG_ERR("Failed to write SysConfig1");
792 return rc;
793 }
794
795 /* Relative mode features */
796 if (config->relative_mode) {
797 value = (PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE |
798 PINNACLE_FEED_CONFIG2_SCROLL_DISABLE |
799 PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE);
800 if (config->swap_xy) {
801 value |= PINNACLE_FEED_CONFIG2_SWAP_X_AND_Y;
802 }
803 if (!config->primary_tap_enabled) {
804 value |= PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE;
805 }
806 } else {
807 value = (PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE |
808 PINNACLE_FEED_CONFIG2_SCROLL_DISABLE |
809 PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE |
810 PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE);
811 }
812 rc = pinnacle_write(dev, PINNACLE_REG_FEED_CONFIG2, value);
813 if (rc) {
814 LOG_ERR("Failed to write FeedConfig2");
815 return rc;
816 }
817
818 /* Data output flags */
819 value = PINNACLE_FEED_CONFIG1_FEED_ENABLE;
820 if (!config->relative_mode) {
821 value |= PINNACLE_FEED_CONFIG1_DATA_MODE_ABSOLUTE;
822 if (config->invert_x) {
823 value |= PINNACLE_FEED_CONFIG1_X_INVERT;
824 }
825 if (config->invert_y) {
826 value |= PINNACLE_FEED_CONFIG1_Y_INVERT;
827 }
828 }
829 rc = pinnacle_write(dev, PINNACLE_REG_FEED_CONFIG1, value);
830 if (rc) {
831 LOG_ERR("Failed to enable Feed in FeedConfig1");
832 return rc;
833 }
834
835 /* Configure count of Z-Idle packets */
836 rc = pinnacle_write(dev, PINNACLE_REG_Z_IDLE, config->idle_packets_count);
837 if (rc) {
838 LOG_ERR("Failed to set count of Z-idle packets");
839 return rc;
840 }
841
842 rc = pinnacle_init_interrupt(dev);
843 if (rc) {
844 LOG_ERR("Failed to initialize interrupts");
845 return rc;
846 }
847
848 return 0;
849 }
850
851 #define PINNACLE_CONFIG_BUS_I2C(inst) \
852 .bus = { \
853 .i2c = I2C_DT_SPEC_INST_GET(inst), \
854 .is_ready = pinnacle_is_ready_i2c, \
855 .write = pinnacle_write_i2c, \
856 .seq_write = pinnacle_seq_write_i2c, \
857 .read = pinnacle_read_i2c, \
858 .seq_read = pinnacle_seq_read_i2c, \
859 }
860
861 #define PINNACLE_SPI_OP (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_MODE_CPHA | SPI_WORD_SET(8))
862 #define PINNACLE_CONFIG_BUS_SPI(inst) \
863 .bus = { \
864 .spi = SPI_DT_SPEC_INST_GET(inst, PINNACLE_SPI_OP, 0U), \
865 .is_ready = pinnacle_is_ready_spi, \
866 .write = pinnacle_write_spi, \
867 .seq_write = pinnacle_seq_write_spi, \
868 .read = pinnacle_read_spi, \
869 .seq_read = pinnacle_seq_read_spi, \
870 }
871
872 #define PINNACLE_DEFINE(inst) \
873 static const struct pinnacle_config pinnacle_config_##inst = { \
874 COND_CODE_1(DT_INST_ON_BUS(inst, i2c), (PINNACLE_CONFIG_BUS_I2C(inst),), ()) \
875 COND_CODE_1(DT_INST_ON_BUS(inst, spi), (PINNACLE_CONFIG_BUS_SPI(inst),), ()) \
876 .dr_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, data_ready_gpios, {}), \
877 .relative_mode = DT_INST_ENUM_IDX(inst, data_mode), \
878 .sensitivity = DT_INST_ENUM_IDX(inst, sensitivity), \
879 .idle_packets_count = DT_INST_PROP(inst, idle_packets_count), \
880 .clipping_enabled = DT_INST_PROP(inst, clipping_enable), \
881 .active_range_x_min = DT_INST_PROP(inst, active_range_x_min), \
882 .active_range_x_max = DT_INST_PROP(inst, active_range_x_max), \
883 .active_range_y_min = DT_INST_PROP(inst, active_range_y_min), \
884 .active_range_y_max = DT_INST_PROP(inst, active_range_y_max), \
885 .scaling_enabled = DT_INST_PROP(inst, scaling_enable), \
886 .resolution_x = DT_INST_PROP(inst, scaling_x_resolution), \
887 .resolution_y = DT_INST_PROP(inst, scaling_y_resolution), \
888 .invert_x = DT_INST_PROP(inst, invert_x), \
889 .invert_y = DT_INST_PROP(inst, invert_y), \
890 .primary_tap_enabled = DT_INST_PROP(inst, primary_tap_enable), \
891 .swap_xy = DT_INST_PROP(inst, swap_xy), \
892 }; \
893 static struct pinnacle_data pinnacle_data_##inst; \
894 DEVICE_DT_INST_DEFINE(inst, pinnacle_init, NULL, &pinnacle_data_##inst, \
895 &pinnacle_config_##inst, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
896 NULL); \
897 BUILD_ASSERT(DT_INST_PROP(inst, active_range_x_min) < \
898 DT_INST_PROP(inst, active_range_x_max), \
899 "active-range-x-min must be less than active-range-x-max"); \
900 BUILD_ASSERT(DT_INST_PROP(inst, active_range_y_min) < \
901 DT_INST_PROP(inst, active_range_y_max), \
902 "active_range-y-min must be less than active_range-y-max"); \
903 BUILD_ASSERT(DT_INST_PROP(inst, scaling_x_resolution) > 0, \
904 "scaling-x-resolution must be positive"); \
905 BUILD_ASSERT(DT_INST_PROP(inst, scaling_y_resolution) > 0, \
906 "scaling-y-resolution must be positive"); \
907 BUILD_ASSERT(IN_RANGE(DT_INST_PROP(inst, idle_packets_count), 0, UINT8_MAX), \
908 "idle-packets-count must be in range [0:255]");
909
910 DT_INST_FOREACH_STATUS_OKAY(PINNACLE_DEFINE)
911
