1 /* 2 * Copyright (c) 2021 Andes Technology Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __RISCV_ANDES_V5_SOC_V5_H_ 8 #define __RISCV_ANDES_V5_SOC_V5_H_ 9 10 /* Control and Status Registers (CSRs) available for Andes V5 SoCs */ 11 #define NDS_MMISC_CTL 0x7D0 12 #define NDS_MCACHE_CTL 0x7CA 13 #define NDS_MXSTATUS 0x7C4 14 #define NDS_MCCTLBEGINADDR 0x7CB 15 #define NDS_MCCTLCOMMAND 0x7CC 16 #define NDS_MCCTLDATA 0x7CD 17 #define NDS_UITB 0x800 18 #define NDS_UCODE 0x801 19 #define NDS_UCCTLBEGINADDR 0x80B 20 #define NDS_UCCTLCOMMAND 0x80C 21 #define NDS_MICM_CFG 0xFC0 22 #define NDS_MDCM_CFG 0xFC1 23 #define NDS_MMSC_CFG 0xFC2 24 #define NDS_MMSC_CFG2 0xFC3 25 #define NDS_MRVARCH_CFG 0xFCA 26 27 /* Control and Status Registers (CSRs) available for Andes V5 PMA */ 28 #define NDS_PMACFG0 0xBC0 29 #define NDS_PMACFG1 0xBC1 30 #define NDS_PMACFG2 0xBC2 31 #define NDS_PMACFG3 0xBC3 32 #define NDS_PMAADDR0 0xBD0 33 #define NDS_PMAADDR1 0xBD1 34 #define NDS_PMAADDR2 0xBD2 35 #define NDS_PMAADDR3 0xBD3 36 #define NDS_PMAADDR4 0xBD4 37 #define NDS_PMAADDR5 0xBD5 38 #define NDS_PMAADDR6 0xBD6 39 #define NDS_PMAADDR7 0xBD7 40 #define NDS_PMAADDR8 0xBD8 41 #define NDS_PMAADDR9 0xBD9 42 #define NDS_PMAADDR10 0xBDA 43 #define NDS_PMAADDR11 0xBDB 44 #define NDS_PMAADDR12 0xBDC 45 #define NDS_PMAADDR13 0xBDD 46 #define NDS_PMAADDR14 0xBDE 47 #define NDS_PMAADDR15 0xBDF 48 49 #endif /* __RISCV_ANDES_V5_SOC_V5_H_ */ 50
