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Searched refs:MIO_PIN_TRI_ENABLE_MASK (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.7.0/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h43 #define MIO_PIN_TRI_ENABLE_MASK BIT(0) macro
44 #define MIO_PIN_TRI_ENABLE(val) FIELD_PREP(MIO_PIN_TRI_ENABLE_MASK, val)
427 (MIO_PIN_PULLUP_MASK | MIO_PIN_TRI_ENABLE_MASK), (0U)) | \