1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Definitions for IEEE 802.3 management interface 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_NET_MDIO_H_ 13 #define ZEPHYR_INCLUDE_NET_MDIO_H_ 14 15 /** 16 * @brief Definitions for IEEE 802.3 management interface 17 * @defgroup ethernet_mdio IEEE 802.3 management interface 18 * @since 3.5 19 * @version 0.8.0 20 * @ingroup ethernet 21 * @{ 22 */ 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /** MDIO transaction operation code */ 29 enum mdio_opcode { 30 /** IEEE 802.3 22.2.4.5.4 write operation */ 31 MDIO_OP_C22_WRITE = 1, 32 33 /** IEEE 802.3 22.2.4.5.4 read operation */ 34 MDIO_OP_C22_READ = 2, 35 36 /** IEEE 802.3 45.3.4 address operation */ 37 MDIO_OP_C45_ADDRESS = 0, 38 39 /** IEEE 802.3 45.3.4 write operation */ 40 MDIO_OP_C45_WRITE = 1, 41 42 /** IEEE 802.3 45.3.4 post-read-increment-address operation */ 43 MDIO_OP_C45_READ_INC = 2, 44 45 /** IEEE 802.3 45.3.4 read operation */ 46 MDIO_OP_C45_READ = 3 47 }; 48 49 /* MDIO Manageable Device addresses */ 50 /** Physical Medium Attachment / Physical Medium Dependent */ 51 #define MDIO_MMD_PMAPMD 0x01U 52 /** WAN Interface Sublayer */ 53 #define MDIO_MMD_WIS 0x02U 54 /** Physical Coding Sublayer */ 55 #define MDIO_MMD_PCS 0x03U 56 /** PHY Extender Sublayer */ 57 #define MDIO_MMD_PHYXS 0x04U 58 /** DTE Extender Sublayer */ 59 #define MDIO_MMD_DTEXS 0x05U 60 /** Transmission Convergence */ 61 #define MDIO_MMD_TC 0x06U 62 /** Auto-negotiation */ 63 #define MDIO_MMD_AN 0x07U 64 /** Separated PMA (1) */ 65 #define MDIO_MMD_SEPARATED_PMA1 0x08U 66 /** Separated PMA (2) */ 67 #define MDIO_MMD_SEPARATED_PMA2 0x09U 68 /** Separated PMA (3) */ 69 #define MDIO_MMD_SEPARATED_PMA3 0x0AU 70 /** Separated PMA (4) */ 71 #define MDIO_MMD_SEPARATED_PMA4 0x0BU 72 /** Clause 22 extension */ 73 #define MDIO_MMD_C22EXT 0x1DU 74 /** Vendor Specific 1 */ 75 #define MDIO_MMD_VENDOR_SPECIFIC1 0x1EU 76 /** Vendor Specific 2 */ 77 #define MDIO_MMD_VENDOR_SPECIFIC2 0x1FU 78 79 /* MDIO generic registers */ 80 /** Control 1 */ 81 #define MDIO_CTRL1 0x0000U 82 /** Status 1 */ 83 #define MDIO_STAT1 0x0001U 84 /** Device identifier (1) */ 85 #define MDIO_DEVID1 0x0002U 86 /** Device identifier (2) */ 87 #define MDIO_DEVID2 0x0003U 88 /** Speed ability */ 89 #define MDIO_SPEED 0x0004U 90 /** Devices in package (1) */ 91 #define MDIO_DEVS1 0x0005U 92 /** Devices in package (2) */ 93 #define MDIO_DEVS2 0x0006U 94 /** Control 2 */ 95 #define MDIO_CTRL2 0x0007U 96 /** Status 2 */ 97 #define MDIO_STAT2 0x0008U 98 /** Package identifier (1) */ 99 #define MDIO_PKGID1 0x000EU 100 /** Package identifier (2) */ 101 #define MDIO_PKGID2 0x000FU 102 103 104 /* BASE-T1 registers */ 105 /** BASE-T1 Auto-negotiation control */ 106 #define MDIO_AN_T1_CTRL 0x0200U 107 /** BASE-T1 Auto-negotiation status */ 108 #define MDIO_AN_T1_STAT 0x0201U 109 /** BASE-T1 Auto-negotiation advertisement register [15:0] */ 110 #define MDIO_AN_T1_ADV_L 0x0202U 111 /** BASE-T1 Auto-negotiation advertisement register [31:16] */ 112 #define MDIO_AN_T1_ADV_M 0x0203U 113 /** BASE-T1 Auto-negotiation advertisement register [47:32] */ 114 #define MDIO_AN_T1_ADV_H 0x0204U 115 /** BASE-T1 PMA/PMD control register */ 116 #define MDIO_PMA_PMD_BT1_CTRL 0x0834U 117 118 /* BASE-T1 Auto-negotiation Control register */ 119 /** Auto-negotiation Restart */ 120 #define MDIO_AN_T1_CTRL_RESTART BIT(9) 121 /** Auto-negotiation Enable */ 122 #define MDIO_AN_T1_CTRL_EN BIT(12) 123 124 /* BASE-T1 Auto-negotiation Status register */ 125 /** Link Status */ 126 #define MDIO_AN_T1_STAT_LINK_STATUS BIT(2) 127 /** Auto-negotiation Ability */ 128 #define MDIO_AN_T1_STAT_ABLE BIT(3) 129 /** Auto-negotiation Remote Fault */ 130 #define MDIO_AN_T1_STAT_REMOTE_FAULT BIT(4) 131 /** Auto-negotiation Complete */ 132 #define MDIO_AN_T1_STAT_COMPLETE BIT(5) 133 /** Page Received */ 134 #define MDIO_AN_T1_STAT_PAGE_RX BIT(6) 135 136 /* BASE-T1 Auto-negotiation Advertisement register [15:0] */ 137 /** Pause Ability */ 138 #define MDIO_AN_T1_ADV_L_PAUSE_CAP BIT(10) 139 /** Pause Ability */ 140 #define MDIO_AN_T1_ADV_L_PAUSE_ASYM BIT(11) 141 /** Force Master/Slave Configuration */ 142 #define MDIO_AN_T1_ADV_L_FORCE_MS BIT(12) 143 /** Remote Fault */ 144 #define MDIO_AN_T1_ADV_L_REMOTE_FAULT BIT(13) 145 /** Acknowledge (ACK) */ 146 #define MDIO_AN_T1_ADV_L_ACK BIT(14) 147 /** Next Page Request */ 148 #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ BIT(15) 149 150 /* BASE-T1 Auto-negotiation Advertisement register [31:16] */ 151 /** 10BASE-T1L Ability */ 152 #define MDIO_AN_T1_ADV_M_B10L BIT(14) 153 /** Master/slave Configuration */ 154 #define MDIO_AN_T1_ADV_M_MST BIT(4) 155 156 /* BASE-T1 Auto-negotiation Advertisement register [47:32] */ 157 /** 10BASE-T1L High Level Transmit Operating Mode Request */ 158 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ BIT(12) 159 /** 10BASE-T1L High Level Transmit Operating Mode Ability */ 160 #define MDIO_AN_T1_ADV_H_10L_TX_HI BIT(13) 161 162 /* BASE-T1 PMA/PMD control register */ 163 /** BASE-T1 master/slave configuration */ 164 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST BIT(14) 165 166 167 /* 10BASE-T1L registers */ 168 /** 10BASE-T1L PMA control */ 169 #define MDIO_PMA_B10L_CTRL 0x08F6U 170 /** 10BASE-T1L PMA status */ 171 #define MDIO_PMA_B10L_STAT 0x08F7U 172 /** 10BASE-T1L PMA link status*/ 173 #define MDIO_PMA_B10L_LINK_STAT 0x8302U 174 /** 10BASE-T1L PCS control */ 175 #define MDIO_PCS_B10L_CTRL 0x08E6U 176 /** 10BASE-T1L PCS status */ 177 #define MDIO_PCS_B10L_STAT 0x08E7U 178 179 /* 10BASE-T1L PMA control register */ 180 /** 10BASE-T1L Transmit Disable Mode */ 181 #define MDIO_PMA_B10L_CTRL_TX_DIS_MODE_EN BIT(14) 182 /** 10BASE-T1L Transmit Voltage Amplitude Control */ 183 #define MDIO_PMA_B10L_CTRL_TX_LVL_HI BIT(12) 184 /** 10BASE-T1L EEE Enable */ 185 #define MDIO_PMA_B10L_CTRL_EEE BIT(10) 186 /** 10BASE-T1L PMA Loopback */ 187 #define MDIO_PMA_B10L_CTRL_LB_PMA_LOC_EN BIT(0) 188 189 /* 10BASE-T1L PMA status register */ 190 /** 10BASE-T1L PMA receive link up */ 191 #define MDIO_PMA_B10L_STAT_LINK BIT(0) 192 /** 10BASE-T1L Fault condition detected */ 193 #define MDIO_PMA_B10L_STAT_FAULT BIT(1) 194 /** 10BASE-T1L Receive polarity is reversed */ 195 #define MDIO_PMA_B10L_STAT_POLARITY BIT(2) 196 /** 10BASE-T1L Able to detect fault on receive path */ 197 #define MDIO_PMA_B10L_STAT_RECV_FAULT BIT(9) 198 /** 10BASE-T1L PHY has EEE ability */ 199 #define MDIO_PMA_B10L_STAT_EEE BIT(10) 200 /** 10BASE-T1L PMA has low-power ability */ 201 #define MDIO_PMA_B10L_STAT_LOW_POWER BIT(11) 202 /** 10BASE-T1L PHY has 2.4 Vpp operating mode ability */ 203 #define MDIO_PMA_B10L_STAT_2V4_ABLE BIT(12) 204 /** 10BASE-T1L PHY has loopback ability */ 205 #define MDIO_PMA_B10L_STAT_LB_ABLE BIT(13) 206 207 /* 10BASE-T1L PMA link status*/ 208 /** 10BASE-T1L Remote Receiver Status OK Latch Low */ 209 #define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK_LL BIT(9) 210 /** 10BASE-T1L Remote Receiver Status OK */ 211 #define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK BIT(8) 212 /** 10BASE-T1L Local Receiver Status OK */ 213 #define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK_LL BIT(7) 214 /** 10BASE-T1L Local Receiver Status OK */ 215 #define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK BIT(6) 216 /** 10BASE-T1L Descrambler Status OK Latch Low */ 217 #define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK_LL BIT(5) 218 /** 10BASE-T1L Descrambler Status OK */ 219 #define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK BIT(4) 220 /** 10BASE-T1L Link Status OK Latch Low */ 221 #define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK_LL BIT(1) 222 /** 10BASE-T1L Link Status OK */ 223 #define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK BIT(0) 224 225 /* 10BASE-T1L PCS control */ 226 /** 10BASE-T1L PCS Loopback Enable */ 227 #define MDIO_PCS_B10L_CTRL_LB_PCS_EN BIT(14) 228 229 /* 10BASE-T1L PCS status */ 230 /** 10BASE-T1L PCS Descrambler Status */ 231 #define MDIO_PCS_B10L_STAT_DSCR_STAT_OK_LL BIT(2) 232 233 #ifdef __cplusplus 234 } 235 #endif 236 237 /** 238 * @} 239 */ 240 241 #endif /* ZEPHYR_INCLUDE_NET_MDIO_H_ */ 242
