1 /* 2 * Copyright (c) 2024, Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SUBSYS_FPGA_BRIDGE_INTEL_H_ 8 #define ZEPHYR_SUBSYS_FPGA_BRIDGE_INTEL_H_ 9 10 #include <zephyr/kernel.h> 11 12 /* Mask for FPGA-HPS bridges */ 13 #define BRIDGE_MASK 0x0F 14 /* Mailbox command header index */ 15 #define MBOX_CMD_HEADER_INDEX 0x00 16 /* Mailbox command memory size */ 17 #define FPGA_MB_CMD_ADDR_MEM_SIZE 20 18 /* Mailbox command response memory size */ 19 #define FPGA_MB_RESPONSE_MEM_SIZE 20 20 /* Config status response length */ 21 #define FPGA_CONFIG_STATUS_RESPONSE_LEN 0x07 22 23 #define MBOX_CMD_CODE_OFFSET 0x00 24 #define MBOX_CMD_ID_MASK 0x7FF 25 26 #define MBOX_CMD_MODE_OFFSET 0x0B 27 #define MBOX_CMD_MODE_MASK 0x800 28 29 #define MBOX_DATA_LEN_OFFSET 0x0C 30 #define MBOX_DATA_LEN_MASK 0xFFF000 31 32 #define RECONFIG_DIRECT_COUNT_OFFSET 0x00 33 #define RECONFIG_DIRECT_COUNT_MASK 0xFF 34 35 #define RECONFIG_INDIRECT_ARG_OFFSET 0x08 36 #define RECONFIG_INDIRECT_COUNT_MASK 0xFF00 37 38 #define RECONFIG_INDIRECT_RESPONSE_OFFSET 0x10 39 #define RECONFIG_RESPONSE_COUNT_MASK 0xFF0000 40 41 #define RECONFIG_DATA_MB_CMD_SIZE 0x10 42 #define RECONFIG_DATA_MB_CMD_INDIRECT_MODE 0x01 43 44 #define RECONFIG_DATA_MB_CMD_LENGTH 0x03 45 46 #define RECONFIG_DATA_MB_CMD_DIRECT_COUNT 0x00 47 #define RECONFIG_DATA_MB_CMD_INDIRECT_ARG 0x01 48 #define RECONFIG_DATA_MB_CMD_INDIRECT_RESPONSE 0x00 49 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000 50 #define RECONFIG_STATUS_RETRY_COUNT 20 51 52 #define MBOX_CONFIG_STATUS_STATE_CONFIG 0x10000000 53 #define MBOX_CFGSTAT_VAB_BS_PREAUTH 0x20000000 54 55 #define FPGA_NOT_CONFIGURED_ERROR 0x02000004 56 57 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xF0000005 58 #define RECONFIG_SOFTFUNC_STATUS_CONF_DONE BIT(0) 59 #define RECONFIG_SOFTFUNC_STATUS_INIT_DONE BIT(1) 60 #define RECONFIG_SOFTFUNC_STATUS_SEU_ERROR BIT(3) 61 #define RECONFIG_PIN_STATUS_NSTATUS BIT(31) 62 63 #define MBOX_REQUEST_HEADER(cmd_id, cmd_mode, len) \ 64 ((cmd_id << MBOX_CMD_CODE_OFFSET) & (MBOX_CMD_ID_MASK)) | \ 65 ((cmd_mode << MBOX_CMD_MODE_OFFSET) & (MBOX_CMD_MODE_MASK)) | \ 66 ((len << MBOX_DATA_LEN_OFFSET) & (MBOX_DATA_LEN_MASK)) 67 68 #define MBOX_RECONFIG_REQUEST_DATA_FORMAT(direct_count, indirect_arg_count, response_arg_count) \ 69 ((direct_count << RECONFIG_DIRECT_COUNT_OFFSET) & (RECONFIG_DIRECT_COUNT_MASK)) | \ 70 ((indirect_arg_count << RECONFIG_INDIRECT_ARG_OFFSET) & \ 71 (RECONFIG_INDIRECT_COUNT_MASK)) | \ 72 ((response_arg_count << RECONFIG_INDIRECT_RESPONSE_OFFSET) & \ 73 (RECONFIG_RESPONSE_COUNT_MASK)) 74 75 union mailbox_response_header { 76 /* Header of the config status response */ 77 uint32_t header; 78 79 struct { 80 /* error_code – Field provides a basic description of whether the command 81 * succeeded or not. A successful response returns an error code of 0x0, 82 * non-zero values indicate failure 83 */ 84 uint32_t error_code : 11; 85 /* indirect_bit - Field indicates an indirect command */ 86 uint32_t indirect_bit : 1; 87 /* data_length - Field counts the number of word arguments which follow the 88 * response header word. The meaning of these words depends on the command 89 * code. Units are words 90 */ 91 uint32_t data_length : 11; 92 /* reserve bit */ 93 uint32_t reserved_bit : 1; 94 /* id - Field is returned unchanged from the matching command header and is 95 * useful for matching responses to commands along with the CLIENT 96 */ 97 uint32_t id : 4; 98 /* client_id - Field is returned unchanged from the matching command header and 99 * is useful for matching responses to commands along with the ID 100 */ 101 uint32_t client_id : 4; 102 } mailbox_resp_header; 103 }; 104 105 union config_status_version { 106 /* Version of the config status response */ 107 uint32_t version; 108 109 struct { 110 /* update number bits */ 111 uint32_t update_number : 8; 112 /* minor acds release number bits */ 113 uint32_t minor_acds_release_number : 8; 114 /* major acds release number bits */ 115 uint32_t major_acds_release_number : 8; 116 /* qspi flash index bits */ 117 uint32_t qspi_flash_index : 8; 118 } response_version_member; 119 }; 120 121 union config_status_pin_status { 122 uint32_t pin_status; 123 124 struct { 125 /* msel bits */ 126 uint32_t msel : 4; 127 /* pmf data bits */ 128 uint32_t pmf_data : 4; 129 /* reserve bits */ 130 uint32_t reserved_bit : 22; 131 /* nconfig bits */ 132 uint32_t nconfig : 1; 133 /* nconfig_status bits */ 134 uint32_t nconfig_status : 1; 135 } pin_status_member; 136 }; 137 138 /* Struct to store the fpga_config_status */ 139 struct fpga_config_status { 140 /* Response header */ 141 union mailbox_response_header header; 142 /* Config state idle or config mode */ 143 uint32_t state; 144 /* Version number */ 145 union config_status_version version; 146 /* Pin status */ 147 union config_status_pin_status pin_status; 148 /* Soft function status details */ 149 uint32_t soft_function_status; 150 /* Location in the bitstream where the error occurred */ 151 uint32_t error_location; 152 /* Data is non-zero only for certain errors. The contents are highly dependent 153 * on which error was reported. The meaning of this data will not be made available to 154 * customers and can only be interpreted by investigating the source code directly 155 */ 156 uint32_t error_details; 157 }; 158 159 enum smc_cmd_code { 160 /* SMC COMMAND ID to disable all the bridges */ 161 FPGA_ALL_BRIDGE_DISABLE = 0x00, 162 /* SMC COMMAND ID to enable all the bridges */ 163 FPGA_ALL_BRIDGE_ENABLE = 0x01, 164 /* SMC Cancel Command */ 165 FPGA_CANCEL = 0x03, 166 /* SMC COMMAND ID to check Reconfig status to SDM via mailbox */ 167 FPGA_CONFIG_STATUS = 0x04, 168 /* SMC COMMAND ID to check Reconfig status to SDM via mailbox */ 169 FPGA_RECONFIG_STATUS = 0x09 170 }; 171 172 enum mbox_reconfig_status_resp { 173 /* Mailbox reconfig status header */ 174 MBOX_RECONFIG_STATUS_HEADER, 175 /* Mailbox reconfig status state */ 176 MBOX_RECONFIG_STATUS_STATE, 177 /* Mailbox reconfig status version */ 178 MBOX_RECONFIG_STATUS_VERSION, 179 /* Mailbox reconfig status pin status */ 180 MBOX_RECONFIG_STATUS_PIN_STATUS, 181 /* Mailbox reconfig status soft function */ 182 MBOX_RECONFIG_STATUS_SOFT_FUNCTION, 183 /* Mailbox reconfig status error location */ 184 MBOX_RECONFIG_STATUS_ERROR_LOCATION, 185 /* Mailbox reconfig status error details */ 186 MBOX_RECONFIG_STATUS_ERROR_DETAILS 187 }; 188 189 enum smc_request { 190 /* SMC request parameter a2 index*/ 191 SMC_REQUEST_A2_INDEX = 0x00, 192 /* SMC request parameter a3 index */ 193 SMC_REQUEST_A3_INDEX = 0x01 194 }; 195 196 /* SIP SVC response private data */ 197 struct sip_svc_private_data { 198 struct sip_svc_response response; 199 uint32_t *mbox_response_data; 200 uint32_t mbox_response_len; 201 struct k_sem smc_sem; 202 struct fpga_config_status config_status; 203 }; 204 205 #endif 206
