1 /* 2 * Copyright (c) 2022 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_UHC_MAX3421E_H 8 #define ZEPHYR_INCLUDE_UHC_MAX3421E_H 9 10 #include <zephyr/sys/util_macro.h> 11 12 #define MAX3421E_MAX_EP_SIZE 64U 13 14 15 /* SPI command byte format macros */ 16 #define MAX3421E_CMD_REG_SHIFT 3U 17 #define MAX3421E_CMD_DIR_WR BIT(1) 18 #define MAX3421E_CMD_DIR_RD 0U 19 20 #define MAX3421E_CMD_SPI_READ(reg) \ 21 (((reg) << MAX3421E_CMD_REG_SHIFT) | MAX3421E_CMD_DIR_RD) 22 23 #define MAX3421E_CMD_SPI_WRITE(reg) \ 24 (((reg) << MAX3421E_CMD_REG_SHIFT) | MAX3421E_CMD_DIR_WR) 25 26 27 /* Below are all the register definitions for the host mode. */ 28 29 /* Register RCVFIFO */ 30 #define MAX3421E_REG_RCVFIFO 1U 31 32 /* Register SNDFIFO */ 33 #define MAX3421E_REG_SNDFIFO 2U 34 35 /* Register SUDFIFO */ 36 #define MAX3421E_REG_SUDFIFO 4U 37 38 /* Register RCVBC */ 39 #define MAX3421E_REG_RCVBC 6U 40 #define MAX3421E_RCVBC_MAX 0x7FU 41 42 /* Register SNDBC */ 43 #define MAX3421E_REG_SNDBC 7U 44 #define MAX3421E_SNDBC_MAX 0x7FU 45 46 /* Register USBIRQ */ 47 #define MAX3421E_REG_USBIRQ 13U 48 #define MAX3421E_VBUSIRQ BIT(6) 49 #define MAX3421E_NOVBUSIRQ BIT(5) 50 #define MAX3421E_OSCOKIRQ BIT(0) 51 52 /* Register USBIEN */ 53 #define MAX3421E_REG_USBIEN 14U 54 #define MAX3421E_VBUSIE BIT(6) 55 #define MAX3421E_NOVBUSIE BIT(5) 56 #define MAX3421E_OSCOKIE BIT(0) 57 58 /* Register USBCTL */ 59 #define MAX3421E_REG_USBCTL 15U 60 #define MAX3421E_CHIPRES BIT(5) 61 #define MAX3421E_PWRDOWN BIT(4) 62 63 /* Register CPUCTL */ 64 #define MAX3421E_REG_CPUCTL 16U 65 #define MAX3421E_PULSEWID1 BIT(7) 66 #define MAX3421E_PULSEWID0 BIT(6) 67 #define MAX3421E_IE BIT(0) 68 69 /* Register PINCTL */ 70 #define MAX3421E_REG_PINCTL 17U 71 #define MAX3421E_FDUPSPI BIT(4) 72 #define MAX3421E_INTLEVEL BIT(3) 73 #define MAX3421E_POSINT BIT(2) 74 #define MAX3421E_GPXB BIT(1) 75 #define MAX3421E_GPXA BIT(0) 76 77 /* Register REVISION */ 78 #define MAX3421E_REG_REVISION 18U 79 80 /* Register IOPINS1, IOPINS2, GPINIRQ, GPINIEN, GPINPOL */ 81 #define MAX3421E_REG_IOPINS1 20U 82 #define MAX3421E_REG_IOPINS2 21U 83 #define MAX3421E_REG_GPINIRQ 22U 84 #define MAX3421E_REG_GPINIE 23U 85 #define MAX3421E_REG_GPINPOL 24U 86 87 /* Register HIRQ and HIEN */ 88 #define MAX3421E_REG_HIRQ 25U 89 #define MAX3421E_REG_HIEN 26U 90 #define MAX3421E_HXFRDN BIT(7) 91 #define MAX3421E_FRAME BIT(6) 92 #define MAX3421E_CONDET BIT(5) 93 #define MAX3421E_SUSDN BIT(4) 94 #define MAX3421E_SNDBAV BIT(3) 95 #define MAX3421E_RCVDAV BIT(2) 96 #define MAX3421E_RWU BIT(1) 97 #define MAX3421E_BUSEVENT BIT(0) 98 99 /* Register MODE */ 100 #define MAX3421E_REG_MODE 27U 101 #define MAX3421E_DPPULLDN BIT(7) 102 #define MAX3421E_DMPULLDN BIT(6) 103 #define MAX3421E_DELAYISO BIT(5) 104 #define MAX3421E_SEPIRQ BIT(4) 105 #define MAX3421E_SOFKAENAB BIT(3) 106 #define MAX3421E_HUBPRE BIT(2) 107 #define MAX3421E_LOWSPEED BIT(1) 108 #define MAX3421E_HOST BIT(0) 109 110 /* Register PERADDR */ 111 #define MAX3421E_REG_PERADDR 28U 112 #define MAX3421E_PERADDR_MASK 0x7FU 113 114 /* Register HCTL */ 115 #define MAX3421E_REG_HCTL 29U 116 #define MAX3421E_SNDTOG1 BIT(7) 117 #define MAX3421E_SNDTOG0 BIT(6) 118 #define MAX3421E_RCVTOG1 BIT(5) 119 #define MAX3421E_RCVTOG0 BIT(4) 120 #define MAX3421E_SIGRSM BIT(3) 121 #define MAX3421E_SAMPLEBUS BIT(2) 122 #define MAX3421E_FRMRST BIT(1) 123 #define MAX3421E_BUSRST BIT(0) 124 125 /* Register HXFR */ 126 #define MAX3421E_REG_HXFR 30U 127 #define MAX3421E_HS BIT(7) 128 #define MAX3421E_ISO BIT(6) 129 #define MAX3421E_OUTNIN BIT(5) 130 #define MAX3421E_SETUP BIT(4) 131 #define MAX3421E_EP_MASK 0x0FU 132 #define MAX3421E_EP(ep) ((ep) & MAX3421E_EP_MASK) 133 #define MAX3421E_HXFR_TYPE(hxfr) ((hxfr) & 0xF0U) 134 135 #define MAX3421E_HXFR_SETUP(ep) (MAX3421E_SETUP | MAX3421E_EP(ep)) 136 137 #define MAX3421E_HXFR_BULKIN(ep) MAX3421E_EP(ep) 138 #define MAX3421E_HXFR_ISOIN(ep) (MAX3421E_ISO | MAX3421E_EP(ep)) 139 #define MAX3421E_HXFR_HSIN(ep) (MAX3421E_HS | MAX3421E_EP(ep)) 140 141 #define MAX3421E_HXFR_BULKOUT(ep) (MAX3421E_OUTNIN | MAX3421E_HXFR_BULKIN(ep)) 142 #define MAX3421E_HXFR_ISOOUT(ep) (MAX3421E_OUTNIN | MAX3421E_HXFR_ISOIN(ep)) 143 #define MAX3421E_HXFR_HSOUT(ep) (MAX3421E_OUTNIN | MAX3421E_HXFR_HSIN(ep)) 144 145 #define MAX3421E_HXFR_TYPE_SETUP MAX3421E_SETUP 146 #define MAX3421E_HXFR_TYPE_HSIN MAX3421E_HS 147 #define MAX3421E_HXFR_TYPE_HSOUT (MAX3421E_OUTNIN | MAX3421E_HXFR_TYPE_HSIN) 148 #define MAX3421E_HXFR_TYPE_ISOIN MAX3421E_ISO 149 #define MAX3421E_HXFR_TYPE_ISOOUT (MAX3421E_OUTNIN | MAX3421E_HXFR_TYPE_ISOIN) 150 #define MAX3421E_HXFR_TYPE_BULKIN 0 151 #define MAX3421E_HXFR_TYPE_BULKOUT MAX3421E_OUTNIN 152 153 /* Register HRSL */ 154 #define MAX3421E_REG_HRSL 31U 155 #define MAX3421E_JKSTATUS_MASK (BIT(7) | BIT(6)) 156 #define MAX3421E_JSTATUS BIT(7) 157 #define MAX3421E_KSTATUS BIT(6) 158 #define MAX3421E_SNDTOGRD BIT(5) 159 #define MAX3421E_RCVTOGRD BIT(4) 160 #define MAX3421E_HRSLT_MASK 0x0FU 161 #define MAX3421E_HRSLT(hr) ((hr) & MAX3421E_HRSLT_MASK) 162 163 #define MAX3421E_HR_SUCCESS 0x00U 164 #define MAX3421E_HR_BUSY 0x01U 165 #define MAX3421E_HR_BADREQ 0x02U 166 #define MAX3421E_HR_UNDEF 0x03U 167 #define MAX3421E_HR_NAK 0x04U 168 #define MAX3421E_HR_STALL 0x05U 169 #define MAX3421E_HR_TOGERR 0x06U 170 #define MAX3421E_HR_WRONGPID 0x07U 171 #define MAX3421E_HR_BADBC 0x08U 172 #define MAX3421E_HR_PIDERR 0x09U 173 #define MAX3421E_HR_PKTERR 0x0AU 174 #define MAX3421E_HR_CRCERR 0x0BU 175 #define MAX3421E_HR_KERR 0x0CU 176 #define MAX3421E_HR_JERR 0x0DU 177 #define MAX3421E_HR_TIMEOUT 0x0EU 178 #define MAX3421E_HR_BABBLE 0x0FU 179 180 /* Successful Transfer */ 181 #define HRSLT_IS_SUCCESS(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_SUCCESS) 182 /* SIE is busy, transfer pending */ 183 #define HRSLT_IS_BUSY(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BUSY) 184 /* Bad value in HXFR reg */ 185 #define HRSLT_IS_BADREQ(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BADREQ) 186 /* reserved */ 187 #define HRSLT_IS_UNDEF(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_UNDEF) 188 /* Peripheral returned NAK */ 189 #define HRSLT_IS_NAK(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_NAK) 190 /* Peripheral returned STALL */ 191 #define HRSLT_IS_STALL(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_STALL) 192 /* Toggle error/ISO over-underrun */ 193 #define HRSLT_IS_TOGERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_TOGERR) 194 /* Received the wrong PID */ 195 #define HRSLT_IS_WRONGPID(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_WRONGPID) 196 /* Bad byte count */ 197 #define HRSLT_IS_BADBC(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BADBC) 198 /* Receive PID is corrupted */ 199 #define HRSLT_IS_PIDERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_PIDERR) 200 /* Packet error (stuff, EOP) */ 201 #define HRSLT_IS_PKTERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_PKTERR) 202 /* CRC error */ 203 #define HRSLT_IS_CRCERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_CRCERR) 204 /* K-state instead of response */ 205 #define HRSLT_IS_KERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_KERR) 206 /* J-state instead of response */ 207 #define HRSLT_IS_JERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_JERR) 208 /* Device did not respond in time */ 209 #define HRSLT_IS_TIMEOUT(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_TIMEOUT) 210 /* Device talked too long */ 211 #define HRSLT_IS_BABBLE(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BABBLE) 212 213 #endif /* ZEPHYR_INCLUDE_UHC_MAX3421E_H */ 214
