1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_TACH_H 8 #define _MEC_TACH_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define MCHP_TACH_INST_SPACING 0x10ul 14 #define MCHP_TACH_INST_SPACING_P2 4u 15 16 /* TACH Control register */ 17 #define MCHP_TACH_CONTROL_REG_OFS 0U 18 #define MCHP_TACH_CONTROL_MASK 0xffffdd03U 19 20 /* Enable exceed high or low limit detection */ 21 #define MCHP_TACH_CTRL_EXCEED_LIM_EN_POS 0 22 #define MCHP_TACH_CTRL_EXCEED_LIM_EN BIT(0) 23 24 /* Enable TACH operation */ 25 #define MCHP_TACH_CTRL_EN_POS 1 26 #define MCHP_TACH_CTRL_EN BIT(MCHP_TACH_CTRL_EN_POS) 27 28 /* Enable input filter */ 29 #define MCHP_TACH_CTRL_FILTER_EN_POS 8 30 #define MCHP_TACH_CTRL_FILTER_EN BIT(MCHP_TACH_CTRL_FILTER_EN_POS) 31 32 /* Select read mode. Latch data on rising edge of selected trigger */ 33 #define MCHP_TACH_CTRL_READ_MODE_SEL_POS 10 34 #define MCHP_TACH_CTRL_READ_MODE_INPUT 0U 35 #define MCHP_TACH_CTRL_READ_MODE_100K_CLOCK BIT(10) 36 37 /* Select TACH edges for counter increment */ 38 #define MCHP_TACH_CTRL_NUM_EDGES_POS 11 39 #define MCHP_TACH_CTRL_NUM_EDGES_MASK0 0x03U 40 #define MCHP_TACH_CTRL_NUM_EDGES_MASK SHLU32(0x03U, 11) 41 #define MCHP_TACH_CTRL_EDGES_2 0U 42 #define MCHP_TACH_CTRL_EDGES_3 SHLU32(1u, 11) 43 #define MCHP_TACH_CTRL_EDGES_5 SHLU32(2u, 11) 44 #define MCHP_TACH_CTRL_EDGES_9 SHLU32(3u, 11) 45 46 /* Enable count ready interrupt */ 47 #define MCHP_TACH_CTRL_CNT_RDY_INT_EN_POS 14 48 #define MCHP_TACH_CTRL_CNT_RDY_INT_EN BIT(14) 49 50 /* Enable input toggle interrupt */ 51 #define MCHP_TACH_CTRL_TOGGLE_INT_EN_POS 15 52 #define MCHP_TACH_CTRL_TOGGLE_INT_EN BIT(15) 53 54 /* Read-only latched TACH pulse counter */ 55 #define MCHP_TACH_CTRL_COUNTER_POS 16 56 #define MCHP_TACH_CTRL_COUNTER_MASK0 0xfffful 57 #define MCHP_TACH_CTRL_COUNTER_MASK SHLU32(0xffffU, 16) 58 59 /* 60 * TACH Status register 61 * bits[0, 2-3] are R/W1C 62 * bit[1] is Read-Only 63 */ 64 #define MCHP_TACH_STATUS_REG_OFS 4U 65 #define MCHP_TACH_STATUS_MASK 0x0FU 66 #define MCHP_TACH_STS_EXCEED_LIMIT_POS 0 67 #define MCHP_TACH_STS_EXCEED_LIMIT BIT(MCHP_TACH_STS_EXCEED_LIMIT_POS) 68 #define MCHP_TACH_STS_PIN_STATE_POS 1 69 #define MCHP_TACH_STS_PIN_STATE_HI BIT(MCHP_TACH_STS_PIN_STATE_POS) 70 #define MCHP_TACH_STS_TOGGLE_POS 2 71 #define MCHP_TACH_STS_TOGGLE BIT(MCHP_TACH_STS_TOGGLE_POS) 72 #define MCHP_TACH_STS_CNT_RDY_POS 3 73 #define MCHP_TACH_STS_CNT_RDY BIT(MCHP_TACH_STS_CNT_RDY_POS) 74 75 /* TACH High Limit Register */ 76 #define MCHP_TACH_HI_LIMIT_REG_OFS 8U 77 #define MCHP_TACH_HI_LIMIT_MASK 0xffffU 78 79 /* TACH Low Limit Register */ 80 #define MCHP_TACH_LO_LIMIT_REG_OFS 0x0CU 81 #define MCHP_TACH_LO_LIMIT_MASK 0xffffU 82 83 /** @brief Tachometer Registers (TACH) */ 84 struct tach_regs { 85 volatile uint32_t CONTROL; 86 volatile uint32_t STATUS; 87 volatile uint32_t LIMIT_HI; 88 volatile uint32_t LIMIT_LO; 89 }; 90 91 #endif /* #ifndef _MEC_TACH_H */ 92
