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Searched refs:INTR_STATUS (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/drivers/i3c/
Di3c_dw.c135 #define INTR_STATUS 0x3c macro
1354 status = sys_read32(config->regs + INTR_STATUS); in i3c_dw_irq()
1359 sys_write32(INTR_TRANSFER_ERR_STAT, config->regs + INTR_STATUS); in i3c_dw_irq()
1381 sys_write32(INTR_READ_REQ_RECV_STAT, config->regs + INTR_STATUS); in i3c_dw_irq()
1387 sys_write32(INTR_IBI_UPDATED_STAT, config->regs + INTR_STATUS); in i3c_dw_irq()
1392 sys_write32(INTR_DYN_ADDR_ASSGN_STAT, config->regs + INTR_STATUS); in i3c_dw_irq()
1618 sys_write32(INTR_ALL, config->regs + INTR_STATUS); in enable_interrupts()
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.h139 #define INTR_STATUS (0x0110) macro
Dflash_cadence_nand_ll.c341 sys_write32(CLEAR_ALL_INTERRUPT, (base_address + INTR_STATUS)); in cdns_nand_transfer_config()
934 if (!WAIT_FOR(((sys_read32(base_address + INTR_STATUS) & BIT(SDMA_TRIGG)) != 0), in cdns_wait_sdma()
939 sys_set_bit((base_address + INTR_STATUS), SDMA_TRIGG); in cdns_wait_sdma()