1 /* dw_i2c.c - I2C file for Design Ware */
2
3 /*
4 * Copyright (c) 2015 Intel Corporation
5 * Copyright (c) 2022 Andrei-Edward Popa
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9 #include <stddef.h>
10 #include <zephyr/types.h>
11 #include <stdlib.h>
12 #include <stdbool.h>
13
14 #include <zephyr/drivers/i2c.h>
15 #include <zephyr/kernel.h>
16 #include <zephyr/init.h>
17 #include <zephyr/pm/device.h>
18 #include <zephyr/arch/cpu.h>
19 #include <string.h>
20
21 #if defined(CONFIG_PINCTRL)
22 #include <zephyr/drivers/pinctrl.h>
23 #endif
24 #if defined(CONFIG_RESET)
25 #include <zephyr/drivers/reset.h>
26 #endif
27
28 #include <errno.h>
29 #include <zephyr/sys/sys_io.h>
30
31 #include <zephyr/sys/util.h>
32
33 #if defined(CONFIG_I2C_DW_LPSS_DMA)
34 #include <zephyr/drivers/dma.h>
35 #include <zephyr/drivers/dma/dma_intel_lpss.h>
36 #endif
37
38 #ifdef CONFIG_IOAPIC
39 #include <zephyr/drivers/interrupt_controller/ioapic.h>
40 #endif
41
42 #include "i2c_dw.h"
43 #include "i2c_dw_registers.h"
44 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
45 #include <zephyr/logging/log.h>
46 #include <zephyr/irq.h>
47 LOG_MODULE_REGISTER(i2c_dw);
48
49 #include "i2c-priv.h"
50
get_regs(const struct device * dev)51 static inline uint32_t get_regs(const struct device *dev)
52 {
53 return (uint32_t)DEVICE_MMIO_GET(dev);
54 }
55
56 #ifdef CONFIG_I2C_DW_LPSS_DMA
i2c_dw_enable_idma(const struct device * dev,bool enable)57 void i2c_dw_enable_idma(const struct device *dev, bool enable)
58 {
59 uint32_t reg;
60 uint32_t reg_base = get_regs(dev);
61
62 if (enable) {
63 write_dma_cr(DW_IC_DMA_ENABLE, reg_base);
64 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
65 } else {
66 reg = read_dma_cr(reg_base);
67 reg &= ~DW_IC_DMA_ENABLE;
68 write_dma_cr(reg, reg_base);
69 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR);
70 }
71 }
72
cb_i2c_idma_transfer(const struct device * dma,void * user_data,uint32_t channel,int status)73 void cb_i2c_idma_transfer(const struct device *dma, void *user_data,
74 uint32_t channel, int status)
75 {
76 const struct device *dev = (const struct device *)user_data;
77 const struct i2c_dw_rom_config * const rom = dev->config;
78 struct i2c_dw_dev_config *const dw = dev->data;
79
80 dma_stop(rom->dma_dev, channel);
81 i2c_dw_enable_idma(dev, false);
82
83 if (status) {
84 dw->xfr_status = true;
85 } else {
86 dw->xfr_status = false;
87 }
88 }
89
i2c_dw_set_fifo_th(const struct device * dev,uint8_t fifo_depth)90 void i2c_dw_set_fifo_th(const struct device *dev, uint8_t fifo_depth)
91 {
92 uint32_t reg_base = get_regs(dev);
93
94 write_tdlr(fifo_depth, reg_base);
95 write_rdlr(fifo_depth - 1, reg_base);
96 }
97
i2c_dw_dr_phy_addr(const struct device * dev)98 inline void *i2c_dw_dr_phy_addr(const struct device *dev)
99 {
100 struct i2c_dw_dev_config *const dw = dev->data;
101
102 return (void *) (dw->phy_addr + DW_IC_REG_DATA_CMD);
103 }
104
i2c_dw_idma_rx_transfer(const struct device * dev)105 int32_t i2c_dw_idma_rx_transfer(const struct device *dev)
106 {
107 struct i2c_dw_dev_config *const dw = dev->data;
108 const struct i2c_dw_rom_config * const rom = dev->config;
109
110 struct dma_config dma_cfg = { 0 };
111 struct dma_block_config dma_block_cfg = { 0 };
112
113 if (!device_is_ready(rom->dma_dev)) {
114 LOG_DBG("DMA device is not ready");
115 return -ENODEV;
116 }
117
118 dma_cfg.dma_slot = 1U;
119 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
120 dma_cfg.source_data_size = 1U;
121 dma_cfg.dest_data_size = 1U;
122 dma_cfg.source_burst_length = 1U;
123 dma_cfg.dest_burst_length = 1U;
124 dma_cfg.dma_callback = cb_i2c_idma_transfer;
125 dma_cfg.user_data = (void *)dev;
126 dma_cfg.complete_callback_en = 0U;
127 dma_cfg.error_callback_dis = 0U;
128 dma_cfg.block_count = 1U;
129 dma_cfg.head_block = &dma_block_cfg;
130
131 dma_block_cfg.block_size = dw->xfr_len;
132 dma_block_cfg.dest_address = (uint64_t)&dw->xfr_buf[0];
133 dma_block_cfg.source_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
134 dw->xfr_status = false;
135
136 if (dma_config(rom->dma_dev, DMA_INTEL_LPSS_RX_CHAN, &dma_cfg)) {
137 LOG_DBG("Error transfer");
138 return -EIO;
139 }
140
141 if (dma_start(rom->dma_dev, DMA_INTEL_LPSS_RX_CHAN)) {
142 LOG_DBG("Error transfer");
143 return -EIO;
144 }
145
146 i2c_dw_enable_idma(dev, true);
147 i2c_dw_set_fifo_th(dev, 1);
148
149 return 0;
150 }
151
i2c_dw_idma_tx_transfer(const struct device * dev,uint64_t data)152 int32_t i2c_dw_idma_tx_transfer(const struct device *dev,
153 uint64_t data)
154 {
155 const struct i2c_dw_rom_config * const rom = dev->config;
156 struct i2c_dw_dev_config *const dw = dev->data;
157
158 struct dma_config dma_cfg = { 0 };
159 struct dma_block_config dma_block_cfg = { 0 };
160
161 if (!device_is_ready(rom->dma_dev)) {
162 LOG_DBG("DMA device is not ready");
163 return -ENODEV;
164 }
165
166 dma_cfg.dma_slot = 0U;
167 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
168 dma_cfg.source_data_size = 1U;
169 dma_cfg.dest_data_size = 1U;
170 dma_cfg.source_burst_length = 1U;
171 dma_cfg.dest_burst_length = 1U;
172 dma_cfg.dma_callback = cb_i2c_idma_transfer;
173 dma_cfg.user_data = (void *)dev;
174 dma_cfg.complete_callback_en = 0U;
175 dma_cfg.error_callback_dis = 0U;
176 dma_cfg.block_count = 1U;
177 dma_cfg.head_block = &dma_block_cfg;
178
179 dma_block_cfg.block_size = 1;
180 dma_block_cfg.source_address = (uint64_t)&data;
181 dma_block_cfg.dest_address = (uint64_t)i2c_dw_dr_phy_addr(dev);
182 dw->xfr_status = false;
183
184 if (dma_config(rom->dma_dev, DMA_INTEL_LPSS_TX_CHAN, &dma_cfg)) {
185 LOG_DBG("Error transfer");
186 return -EIO;
187 }
188
189 if (dma_start(rom->dma_dev, DMA_INTEL_LPSS_TX_CHAN)) {
190 LOG_DBG("Error transfer");
191 return -EIO;
192 }
193 i2c_dw_enable_idma(dev, true);
194 i2c_dw_set_fifo_th(dev, 1);
195
196 return 0;
197 }
198 #endif
199
i2c_dw_data_ask(const struct device * dev)200 static inline void i2c_dw_data_ask(const struct device *dev)
201 {
202 struct i2c_dw_dev_config * const dw = dev->data;
203 uint32_t data;
204 int tx_empty;
205 int rx_empty;
206 int cnt;
207 int rx_buffer_depth, tx_buffer_depth;
208 union ic_comp_param_1_register ic_comp_param_1;
209 uint32_t reg_base = get_regs(dev);
210
211 /* No more bytes to request, so command queue is no longer needed */
212 if (dw->request_bytes == 0U) {
213 clear_bit_intr_mask_tx_empty(reg_base);
214 return;
215 }
216
217 /* Get the FIFO depth that could be from 2 to 256 from HW spec */
218 ic_comp_param_1.raw = read_comp_param_1(reg_base);
219 rx_buffer_depth = ic_comp_param_1.bits.rx_buffer_depth + 1;
220 tx_buffer_depth = ic_comp_param_1.bits.tx_buffer_depth + 1;
221
222 /* How many bytes we can actually ask */
223 rx_empty = (rx_buffer_depth - read_rxflr(reg_base)) - dw->rx_pending;
224
225 if (rx_empty < 0) {
226 /* RX FIFO expected to be full.
227 * So don't request any bytes, yet.
228 */
229 return;
230 }
231
232 /* How many empty slots in TX FIFO (as command queue) */
233 tx_empty = tx_buffer_depth - read_txflr(reg_base);
234
235 /* Figure out how many bytes we can request */
236 cnt = MIN(rx_buffer_depth, dw->request_bytes);
237 cnt = MIN(MIN(tx_empty, rx_empty), cnt);
238
239 while (cnt > 0) {
240 /* Tell controller to get another byte */
241 data = IC_DATA_CMD_CMD;
242
243 /* Send RESTART if needed */
244 if (dw->xfr_flags & I2C_MSG_RESTART) {
245 data |= IC_DATA_CMD_RESTART;
246 dw->xfr_flags &= ~(I2C_MSG_RESTART);
247 }
248
249 /* After receiving the last byte, send STOP if needed */
250 if ((dw->xfr_flags & I2C_MSG_STOP)
251 && (dw->request_bytes == 1U)) {
252 data |= IC_DATA_CMD_STOP;
253 }
254
255 #ifdef CONFIG_I2C_TARGET
256 clear_bit_intr_mask_tx_empty(reg_base);
257 #endif /* CONFIG_I2C_TARGET */
258
259 write_cmd_data(data, reg_base);
260
261 dw->rx_pending++;
262 dw->request_bytes--;
263 cnt--;
264 }
265
266 }
267
i2c_dw_data_read(const struct device * dev)268 static void i2c_dw_data_read(const struct device *dev)
269 {
270 struct i2c_dw_dev_config * const dw = dev->data;
271 uint32_t reg_base = get_regs(dev);
272
273 #ifdef CONFIG_I2C_DW_LPSS_DMA
274 if (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
275 i2c_dw_idma_rx_transfer(dev);
276 dw->xfr_len = 0;
277 dw->rx_pending = 0;
278 }
279 #else
280 while (test_bit_status_rfne(reg_base) && (dw->xfr_len > 0)) {
281 dw->xfr_buf[0] = (uint8_t)read_cmd_data(reg_base);
282
283 dw->xfr_buf++;
284 dw->xfr_len--;
285 dw->rx_pending--;
286
287 if (dw->xfr_len == 0U) {
288 break;
289 }
290 }
291 #endif
292 /* Nothing to receive anymore */
293 if (dw->xfr_len == 0U) {
294 dw->state &= ~I2C_DW_CMD_RECV;
295 return;
296 }
297 }
298
299
i2c_dw_data_send(const struct device * dev)300 static int i2c_dw_data_send(const struct device *dev)
301 {
302 struct i2c_dw_dev_config * const dw = dev->data;
303 uint32_t data = 0U;
304 uint32_t reg_base = get_regs(dev);
305
306 /* Nothing to send anymore, mask the interrupt */
307 if (dw->xfr_len == 0U) {
308 clear_bit_intr_mask_tx_empty(reg_base);
309
310 dw->state &= ~I2C_DW_CMD_SEND;
311
312 return 0;
313 }
314
315 while (test_bit_status_tfnt(reg_base) && (dw->xfr_len > 0)) {
316 /* We have something to transmit to a specific host */
317 data = dw->xfr_buf[0];
318
319 /* Send RESTART if needed */
320 if (dw->xfr_flags & I2C_MSG_RESTART) {
321 data |= IC_DATA_CMD_RESTART;
322 dw->xfr_flags &= ~(I2C_MSG_RESTART);
323 }
324
325 /* Send STOP if needed */
326 if ((dw->xfr_len == 1U) && (dw->xfr_flags & I2C_MSG_STOP)) {
327 data |= IC_DATA_CMD_STOP;
328 }
329
330 #ifdef CONFIG_I2C_DW_LPSS_DMA
331 i2c_dw_idma_tx_transfer(dev, data);
332 #else
333 write_cmd_data(data, reg_base);
334 #endif
335 dw->xfr_len--;
336 dw->xfr_buf++;
337
338 if (test_bit_intr_stat_tx_abrt(reg_base)) {
339 return -EIO;
340 }
341 }
342
343 return 0;
344 }
345
i2c_dw_transfer_complete(const struct device * dev)346 static inline void i2c_dw_transfer_complete(const struct device *dev)
347 {
348 struct i2c_dw_dev_config * const dw = dev->data;
349 uint32_t value;
350 uint32_t reg_base = get_regs(dev);
351
352 write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
353 value = read_clr_intr(reg_base);
354
355 k_sem_give(&dw->device_sync_sem);
356 }
357
358 #ifdef CONFIG_I2C_TARGET
359 static inline uint8_t i2c_dw_read_byte_non_blocking(const struct device *dev);
360 static inline void i2c_dw_write_byte_non_blocking(const struct device *dev, uint8_t data);
361 static void i2c_dw_slave_read_clear_intr_bits(const struct device *dev);
362 #endif
363
i2c_dw_isr(const struct device * port)364 static void i2c_dw_isr(const struct device *port)
365 {
366 struct i2c_dw_dev_config * const dw = port->data;
367 union ic_interrupt_register intr_stat;
368 uint32_t value;
369 int ret = 0;
370 uint32_t reg_base = get_regs(port);
371
372 /* Cache ic_intr_stat for processing, so there is no need to read
373 * the register multiple times.
374 */
375 intr_stat.raw = read_intr_stat(reg_base);
376
377 /*
378 * Causes of an interrupt:
379 * - STOP condition is detected
380 * - Transfer is aborted
381 * - Transmit FIFO is empty
382 * - Transmit FIFO has overflowed
383 * - Receive FIFO is full
384 * - Receive FIFO has overflowed
385 * - Received FIFO has underrun
386 * - Transmit data is required (tx_req)
387 * - Receive data is available (rx_avail)
388 */
389
390 LOG_DBG("I2C: interrupt received");
391
392 /* Check if we are configured as a master device */
393 if (test_bit_con_master_mode(reg_base)) {
394 #ifdef CONFIG_I2C_DW_LPSS_DMA
395 uint32_t stat = sys_read32(reg_base + IDMA_REG_INTR_STS);
396
397 if (stat & IDMA_TX_RX_CHAN_MASK) {
398 const struct i2c_dw_rom_config * const rom = port->config;
399 /* Handle the DMA interrupt */
400 dma_intel_lpss_isr(rom->dma_dev);
401
402 }
403 #endif
404
405 /* Bail early if there is any error. */
406 if ((DW_INTR_STAT_TX_ABRT | DW_INTR_STAT_TX_OVER |
407 DW_INTR_STAT_RX_OVER | DW_INTR_STAT_RX_UNDER) &
408 intr_stat.raw) {
409 dw->state = I2C_DW_CMD_ERROR;
410 goto done;
411 }
412
413 /* Check if the RX FIFO reached threshold */
414 if (intr_stat.bits.rx_full) {
415 i2c_dw_data_read(port);
416 }
417
418 #ifdef CONFIG_I2C_TARGET
419 /* Check if the TX FIFO is ready for commands.
420 * TX FIFO also serves as command queue where read requests
421 * are written to TX FIFO.
422 */
423 if ((dw->xfr_flags & I2C_MSG_RW_MASK)
424 == I2C_MSG_READ) {
425 set_bit_intr_mask_tx_empty(reg_base);
426 }
427 #endif /* CONFIG_I2C_TARGET */
428
429 if (intr_stat.bits.tx_empty) {
430 if ((dw->xfr_flags & I2C_MSG_RW_MASK)
431 == I2C_MSG_WRITE) {
432 ret = i2c_dw_data_send(port);
433 } else {
434 i2c_dw_data_ask(port);
435 }
436
437 /* If STOP is not expected, finish processing this
438 * message if there is nothing left to do anymore.
439 */
440 if (((dw->xfr_len == 0U)
441 && !(dw->xfr_flags & I2C_MSG_STOP))
442 || (ret != 0)) {
443 goto done;
444 }
445
446 }
447
448 /* STOP detected: finish processing this message */
449 if (intr_stat.bits.stop_det) {
450 value = read_clr_stop_det(reg_base);
451 goto done;
452 }
453
454 } else {
455 #ifdef CONFIG_I2C_TARGET
456 const struct i2c_target_callbacks *slave_cb = dw->slave_cfg->callbacks;
457 uint32_t slave_activity = test_bit_status_activity(reg_base);
458 uint8_t data;
459
460 i2c_dw_slave_read_clear_intr_bits(port);
461
462 if (intr_stat.bits.rx_full) {
463 if (dw->state != I2C_DW_CMD_SEND) {
464 dw->state = I2C_DW_CMD_SEND;
465 if (slave_cb->write_requested) {
466 slave_cb->write_requested(dw->slave_cfg);
467 }
468 }
469 /* FIFO needs to be drained here so we don't miss the next interrupt */
470 do {
471 data = i2c_dw_read_byte_non_blocking(port);
472 if (slave_cb->write_received) {
473 slave_cb->write_received(dw->slave_cfg, data);
474 }
475 } while (test_bit_status_rfne(reg_base));
476 }
477
478 if (intr_stat.bits.rd_req) {
479 if (slave_activity) {
480 read_clr_rd_req(reg_base);
481 dw->state = I2C_DW_CMD_RECV;
482 if (slave_cb->read_requested) {
483 slave_cb->read_requested(dw->slave_cfg, &data);
484 i2c_dw_write_byte_non_blocking(port, data);
485 }
486 if (slave_cb->read_processed) {
487 slave_cb->read_processed(dw->slave_cfg, &data);
488 }
489 }
490 }
491 #endif
492 }
493
494 return;
495
496 done:
497 i2c_dw_transfer_complete(port);
498 }
499
500
i2c_dw_setup(const struct device * dev,uint16_t slave_address)501 static int i2c_dw_setup(const struct device *dev, uint16_t slave_address)
502 {
503 struct i2c_dw_dev_config * const dw = dev->data;
504 uint32_t value;
505 union ic_con_register ic_con;
506 union ic_tar_register ic_tar;
507 uint32_t reg_base = get_regs(dev);
508
509 ic_con.raw = 0U;
510
511 /* Disable the device controller to be able set TAR */
512 clear_bit_enable_en(reg_base);
513
514 /* Disable interrupts */
515 write_intr_mask(0, reg_base);
516
517 /* Clear interrupts */
518 value = read_clr_intr(reg_base);
519
520 /* Set master or slave mode - (initialization = slave) */
521 if (I2C_MODE_CONTROLLER & dw->app_config) {
522 /*
523 * Make sure to set both the master_mode and slave_disable_bit
524 * to both 0 or both 1
525 */
526 LOG_DBG("I2C: host configured as Master Device");
527 ic_con.bits.master_mode = 1U;
528 ic_con.bits.slave_disable = 1U;
529 } else {
530 return -EINVAL;
531 }
532
533 ic_con.bits.restart_en = 1U;
534
535 /* Set addressing mode - (initialization = 7 bit) */
536 if (I2C_ADDR_10_BITS & dw->app_config) {
537 LOG_DBG("I2C: using 10-bit address");
538 ic_con.bits.addr_master_10bit = 1U;
539 ic_con.bits.addr_slave_10bit = 1U;
540 }
541
542 /* Setup the clock frequency and speed mode */
543 switch (I2C_SPEED_GET(dw->app_config)) {
544 case I2C_SPEED_STANDARD:
545 LOG_DBG("I2C: speed set to STANDARD");
546 write_ss_scl_lcnt(dw->lcnt, reg_base);
547 write_ss_scl_hcnt(dw->hcnt, reg_base);
548 ic_con.bits.speed = I2C_DW_SPEED_STANDARD;
549
550 break;
551 case I2C_SPEED_FAST:
552 __fallthrough;
553 case I2C_SPEED_FAST_PLUS:
554 LOG_DBG("I2C: speed set to FAST or FAST_PLUS");
555 write_fs_scl_lcnt(dw->lcnt, reg_base);
556 write_fs_scl_hcnt(dw->hcnt, reg_base);
557 ic_con.bits.speed = I2C_DW_SPEED_FAST;
558
559 break;
560 case I2C_SPEED_HIGH:
561 if (!dw->support_hs_mode) {
562 return -EINVAL;
563 }
564
565 LOG_DBG("I2C: speed set to HIGH");
566 write_hs_scl_lcnt(dw->lcnt, reg_base);
567 write_hs_scl_hcnt(dw->hcnt, reg_base);
568 ic_con.bits.speed = I2C_DW_SPEED_HIGH;
569
570 break;
571 default:
572 LOG_DBG("I2C: invalid speed requested");
573 return -EINVAL;
574 }
575
576 LOG_DBG("I2C: lcnt = %d", dw->lcnt);
577 LOG_DBG("I2C: hcnt = %d", dw->hcnt);
578
579 /* Set the IC_CON register */
580 write_con(ic_con.raw, reg_base);
581
582 /* Set RX fifo threshold level.
583 * Setting it to zero automatically triggers interrupt
584 * RX_FULL whenever there is data received.
585 *
586 * TODO: extend the threshold for multi-byte RX.
587 */
588 write_rx_tl(0, reg_base);
589
590 /* Set TX fifo threshold level.
591 * TX_EMPTY interrupt is triggered only when the
592 * TX FIFO is truly empty. So that we can let
593 * the controller do the transfers for longer period
594 * before we need to fill the FIFO again. This may
595 * cause some pauses during transfers, but this keeps
596 * the device from interrupting often.
597 */
598 write_tx_tl(0, reg_base);
599
600 ic_tar.raw = read_tar(reg_base);
601
602 if (test_bit_con_master_mode(reg_base)) {
603 /* Set address of target slave */
604 ic_tar.bits.ic_tar = slave_address;
605 } else {
606 /* Set slave address for device */
607 write_sar(slave_address, reg_base);
608 }
609
610 /* If I2C is being operated in master mode and I2C_DYNAMIC_TAR_UPDATE
611 * configuration parameter is set to Yes (1), the ic_10bitaddr_master
612 * bit in ic_tar register would control whether the DW_apb_i2c starts
613 * its transfers in 7-bit or 10-bit addressing mode.
614 */
615 if (I2C_MODE_CONTROLLER & dw->app_config) {
616 if (I2C_ADDR_10_BITS & dw->app_config) {
617 ic_tar.bits.ic_10bitaddr_master = 1U;
618 } else {
619 ic_tar.bits.ic_10bitaddr_master = 0U;
620 }
621 }
622
623 write_tar(ic_tar.raw, reg_base);
624
625 return 0;
626 }
627
i2c_dw_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t slave_address)628 static int i2c_dw_transfer(const struct device *dev,
629 struct i2c_msg *msgs, uint8_t num_msgs,
630 uint16_t slave_address)
631 {
632 struct i2c_dw_dev_config * const dw = dev->data;
633 struct i2c_msg *cur_msg = msgs;
634 uint8_t msg_left = num_msgs;
635 uint8_t pflags;
636 int ret;
637 uint32_t reg_base = get_regs(dev);
638 uint32_t value = 0;
639
640 __ASSERT_NO_MSG(msgs);
641 if (!num_msgs) {
642 return 0;
643 }
644
645 ret = k_mutex_lock(&dw->bus_mutex, K_FOREVER);
646 if (ret != 0) {
647 return ret;
648 }
649
650 /* First step, check if there is current activity */
651 if (test_bit_status_activity(reg_base) || (dw->state & I2C_DW_BUSY)) {
652 ret = -EBUSY;
653 goto error;
654 }
655
656 dw->state |= I2C_DW_BUSY;
657
658 ret = i2c_dw_setup(dev, slave_address);
659 if (ret) {
660 goto error;
661 }
662
663 /* Enable controller */
664 set_bit_enable_en(reg_base);
665
666 /*
667 * While waiting at device_sync_sem, kernel can switch to idle
668 * task which in turn can call pm_system_suspend() hook of Power
669 * Management App (PMA).
670 * pm_device_busy_set() call here, would indicate to PMA that it should
671 * not execute PM policies that would turn off this ip block, causing an
672 * ongoing hw transaction to be left in an inconsistent state.
673 * Note : This is just a sample to show a possible use of the API, it is
674 * upto the driver expert to see, if he actually needs it here, or
675 * somewhere else, or not needed as the driver's suspend()/resume()
676 * can handle everything
677 */
678 pm_device_busy_set(dev);
679
680 /* Process all the messages */
681 while (msg_left > 0) {
682 /* Workaround for I2C scanner as DW HW does not support 0 byte transfers.*/
683 if ((cur_msg->len == 0) && (cur_msg->buf != NULL)) {
684 cur_msg->len = 1;
685 }
686
687 pflags = dw->xfr_flags;
688
689 dw->xfr_buf = cur_msg->buf;
690 dw->xfr_len = cur_msg->len;
691 dw->xfr_flags = cur_msg->flags;
692 dw->rx_pending = 0U;
693
694 /* Need to RESTART if changing transfer direction */
695 if ((pflags & I2C_MSG_RW_MASK)
696 != (dw->xfr_flags & I2C_MSG_RW_MASK)) {
697 dw->xfr_flags |= I2C_MSG_RESTART;
698 }
699
700 dw->state &= ~(I2C_DW_CMD_SEND | I2C_DW_CMD_RECV);
701
702 if ((dw->xfr_flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
703 dw->state |= I2C_DW_CMD_SEND;
704 dw->request_bytes = 0U;
705 } else {
706 dw->state |= I2C_DW_CMD_RECV;
707 dw->request_bytes = dw->xfr_len;
708 }
709
710 /* Enable interrupts to trigger ISR */
711 if (test_bit_con_master_mode(reg_base)) {
712 /* Enable necessary interrupts */
713 write_intr_mask((DW_ENABLE_TX_INT_I2C_MASTER |
714 DW_ENABLE_RX_INT_I2C_MASTER), reg_base);
715 } else {
716 /* Enable necessary interrupts */
717 write_intr_mask(DW_ENABLE_TX_INT_I2C_SLAVE, reg_base);
718 }
719
720 /* Wait for transfer to be done */
721 ret = k_sem_take(&dw->device_sync_sem, K_MSEC(CONFIG_I2C_DW_RW_TIMEOUT_MS));
722 if (ret != 0) {
723 write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
724 value = read_clr_intr(reg_base);
725 break;
726 }
727
728 if (dw->state & I2C_DW_CMD_ERROR) {
729 ret = -EIO;
730 break;
731 }
732
733 /* Something wrong if there is something left to do */
734 if (dw->xfr_len > 0) {
735 ret = -EIO;
736 break;
737 }
738
739 cur_msg++;
740 msg_left--;
741 }
742
743 pm_device_busy_clear(dev);
744
745 error:
746 dw->state = I2C_DW_STATE_READY;
747 k_mutex_unlock(&dw->bus_mutex);
748
749 return ret;
750 }
751
i2c_dw_runtime_configure(const struct device * dev,uint32_t config)752 static int i2c_dw_runtime_configure(const struct device *dev, uint32_t config)
753 {
754 struct i2c_dw_dev_config * const dw = dev->data;
755 uint32_t value = 0U;
756 uint32_t rc = 0U;
757 uint32_t reg_base = get_regs(dev);
758
759 dw->app_config = config;
760
761 /* Make sure we have a supported speed for the DesignWare model */
762 /* and have setup the clock frequency and speed mode */
763 switch (I2C_SPEED_GET(dw->app_config)) {
764 case I2C_SPEED_STANDARD:
765 /* Following the directions on DW spec page 59, IC_SS_SCL_LCNT
766 * must have register values larger than IC_FS_SPKLEN + 7
767 */
768 if (I2C_STD_LCNT <= (read_fs_spklen(reg_base) + 7)) {
769 value = read_fs_spklen(reg_base) + 8;
770 } else {
771 value = I2C_STD_LCNT;
772 }
773
774 dw->lcnt = value;
775
776 /* Following the directions on DW spec page 59, IC_SS_SCL_HCNT
777 * must have register values larger than IC_FS_SPKLEN + 5
778 */
779 if (I2C_STD_HCNT <= (read_fs_spklen(reg_base) + 5)) {
780 value = read_fs_spklen(reg_base) + 6;
781 } else {
782 value = I2C_STD_HCNT;
783 }
784
785 dw->hcnt = value;
786 break;
787 case I2C_SPEED_FAST:
788 __fallthrough;
789 case I2C_SPEED_FAST_PLUS:
790 /*
791 * Following the directions on DW spec page 59, IC_FS_SCL_LCNT
792 * must have register values larger than IC_FS_SPKLEN + 7
793 */
794 if (I2C_FS_LCNT <= (read_fs_spklen(reg_base) + 7)) {
795 value = read_fs_spklen(reg_base) + 8;
796 } else {
797 value = I2C_FS_LCNT;
798 }
799
800 dw->lcnt = value;
801
802 /*
803 * Following the directions on DW spec page 59, IC_FS_SCL_HCNT
804 * must have register values larger than IC_FS_SPKLEN + 5
805 */
806 if (I2C_FS_HCNT <= (read_fs_spklen(reg_base) + 5)) {
807 value = read_fs_spklen(reg_base) + 6;
808 } else {
809 value = I2C_FS_HCNT;
810 }
811
812 dw->hcnt = value;
813 break;
814 case I2C_SPEED_HIGH:
815 if (dw->support_hs_mode) {
816 if (I2C_HS_LCNT <= (read_hs_spklen(reg_base) + 7)) {
817 value = read_hs_spklen(reg_base) + 8;
818 } else {
819 value = I2C_HS_LCNT;
820 }
821
822 dw->lcnt = value;
823
824 if (I2C_HS_HCNT <= (read_hs_spklen(reg_base) + 5)) {
825 value = read_hs_spklen(reg_base) + 6;
826 } else {
827 value = I2C_HS_HCNT;
828 }
829
830 dw->hcnt = value;
831 } else {
832 rc = -EINVAL;
833 }
834 break;
835 default:
836 /* TODO change */
837 rc = -EINVAL;
838 }
839
840 /*
841 * Clear any interrupts currently waiting in the controller
842 */
843 value = read_clr_intr(reg_base);
844
845 /*
846 * TEMPORARY HACK - The I2C does not work in any mode other than Master
847 * currently. This "hack" forces us to always be configured for master
848 * mode, until we can verify that Slave mode works correctly.
849 */
850 dw->app_config |= I2C_MODE_CONTROLLER;
851
852 return rc;
853 }
854
855 #ifdef CONFIG_I2C_TARGET
i2c_dw_read_byte_non_blocking(const struct device * dev)856 static inline uint8_t i2c_dw_read_byte_non_blocking(const struct device *dev)
857 {
858 uint32_t reg_base = get_regs(dev);
859
860 if (!test_bit_status_rfne(reg_base)) { /* Rx FIFO must not be empty */
861 return -EIO;
862 }
863
864 return (uint8_t)read_cmd_data(reg_base);
865 }
866
i2c_dw_write_byte_non_blocking(const struct device * dev,uint8_t data)867 static inline void i2c_dw_write_byte_non_blocking(const struct device *dev, uint8_t data)
868 {
869 uint32_t reg_base = get_regs(dev);
870
871 if (!test_bit_status_tfnt(reg_base)) { /* Tx FIFO must not be full */
872 return;
873 }
874
875 write_cmd_data(data, reg_base);
876 }
877
i2c_dw_set_master_mode(const struct device * dev)878 static int i2c_dw_set_master_mode(const struct device *dev)
879 {
880 union ic_comp_param_1_register ic_comp_param_1;
881 uint32_t reg_base = get_regs(dev);
882 union ic_con_register ic_con;
883
884 clear_bit_enable_en(reg_base);
885
886 ic_con.bits.master_mode = 1U;
887 ic_con.bits.slave_disable = 1U;
888 ic_con.bits.rx_fifo_full = 0U;
889 write_con(ic_con.raw, reg_base);
890
891 set_bit_enable_en(reg_base);
892
893 ic_comp_param_1.raw = read_comp_param_1(reg_base);
894
895 write_tx_tl(ic_comp_param_1.bits.tx_buffer_depth + 1, reg_base);
896 write_rx_tl(ic_comp_param_1.bits.rx_buffer_depth + 1, reg_base);
897
898 return 0;
899 }
900
i2c_dw_set_slave_mode(const struct device * dev,uint8_t addr)901 static int i2c_dw_set_slave_mode(const struct device *dev, uint8_t addr)
902 {
903 uint32_t reg_base = get_regs(dev);
904 union ic_con_register ic_con;
905
906 ic_con.raw = read_con(reg_base);
907
908 clear_bit_enable_en(reg_base);
909
910 ic_con.bits.master_mode = 0U;
911 ic_con.bits.slave_disable = 0U;
912 ic_con.bits.rx_fifo_full = 1U;
913 ic_con.bits.restart_en = 1U;
914 ic_con.bits.stop_det = 1U;
915
916 write_con(ic_con.raw, reg_base);
917 write_sar(addr, reg_base);
918 write_intr_mask(~DW_INTR_MASK_RESET, reg_base);
919
920 set_bit_enable_en(reg_base);
921
922 write_tx_tl(0, reg_base);
923 write_rx_tl(0, reg_base);
924
925 LOG_DBG("I2C: Host registered as Slave Device");
926
927 return 0;
928 }
929
i2c_dw_slave_register(const struct device * dev,struct i2c_target_config * cfg)930 static int i2c_dw_slave_register(const struct device *dev,
931 struct i2c_target_config *cfg)
932 {
933 struct i2c_dw_dev_config * const dw = dev->data;
934 uint32_t reg_base = get_regs(dev);
935 int ret;
936
937 dw->slave_cfg = cfg;
938 ret = i2c_dw_set_slave_mode(dev, cfg->address);
939 write_intr_mask(DW_INTR_MASK_RX_FULL |
940 DW_INTR_MASK_RD_REQ |
941 DW_INTR_MASK_TX_ABRT |
942 DW_INTR_MASK_STOP_DET, reg_base);
943
944 return ret;
945 }
946
i2c_dw_slave_unregister(const struct device * dev,struct i2c_target_config * cfg)947 static int i2c_dw_slave_unregister(const struct device *dev,
948 struct i2c_target_config *cfg)
949 {
950 struct i2c_dw_dev_config * const dw = dev->data;
951 int ret;
952
953 dw->state = I2C_DW_STATE_READY;
954 ret = i2c_dw_set_master_mode(dev);
955
956 return ret;
957 }
958
i2c_dw_slave_read_clear_intr_bits(const struct device * dev)959 static void i2c_dw_slave_read_clear_intr_bits(const struct device *dev)
960 {
961 struct i2c_dw_dev_config * const dw = dev->data;
962 union ic_interrupt_register intr_stat;
963 uint32_t reg_base = get_regs(dev);
964
965 const struct i2c_target_callbacks *slave_cb = dw->slave_cfg->callbacks;
966
967 intr_stat.raw = read_intr_stat(reg_base);
968
969 if (intr_stat.bits.tx_abrt) {
970 read_clr_tx_abrt(reg_base);
971 dw->state = I2C_DW_STATE_READY;
972 }
973
974 if (intr_stat.bits.rx_under) {
975 read_clr_rx_under(reg_base);
976 dw->state = I2C_DW_STATE_READY;
977 }
978
979 if (intr_stat.bits.rx_over) {
980 read_clr_rx_over(reg_base);
981 dw->state = I2C_DW_STATE_READY;
982 }
983
984 if (intr_stat.bits.tx_over) {
985 read_clr_tx_over(reg_base);
986 dw->state = I2C_DW_STATE_READY;
987 }
988
989 if (intr_stat.bits.rx_done) {
990 read_clr_rx_done(reg_base);
991 dw->state = I2C_DW_STATE_READY;
992 }
993
994 if (intr_stat.bits.activity) {
995 read_clr_activity(reg_base);
996 dw->state = I2C_DW_STATE_READY;
997 }
998
999 if (intr_stat.bits.stop_det) {
1000 read_clr_stop_det(reg_base);
1001 dw->state = I2C_DW_STATE_READY;
1002 if (slave_cb->stop) {
1003 slave_cb->stop(dw->slave_cfg);
1004 }
1005 }
1006
1007 if (intr_stat.bits.start_det) {
1008 read_clr_start_det(reg_base);
1009 dw->state = I2C_DW_STATE_READY;
1010 }
1011
1012 if (intr_stat.bits.gen_call) {
1013 read_clr_gen_call(reg_base);
1014 dw->state = I2C_DW_STATE_READY;
1015 }
1016 }
1017 #endif /* CONFIG_I2C_TARGET */
1018
1019 static const struct i2c_driver_api funcs = {
1020 .configure = i2c_dw_runtime_configure,
1021 .transfer = i2c_dw_transfer,
1022 #ifdef CONFIG_I2C_TARGET
1023 .target_register = i2c_dw_slave_register,
1024 .target_unregister = i2c_dw_slave_unregister,
1025 #endif /* CONFIG_I2C_TARGET */
1026 };
1027
i2c_dw_initialize(const struct device * dev)1028 static int i2c_dw_initialize(const struct device *dev)
1029 {
1030 const struct i2c_dw_rom_config * const rom = dev->config;
1031 struct i2c_dw_dev_config * const dw = dev->data;
1032 union ic_con_register ic_con;
1033 int ret = 0;
1034
1035 #if defined(CONFIG_RESET)
1036 if (rom->reset.dev) {
1037 ret = reset_line_toggle_dt(&rom->reset);
1038 if (ret) {
1039 return ret;
1040 }
1041 }
1042 #endif
1043
1044 #if defined(CONFIG_PINCTRL)
1045 ret = pinctrl_apply_state(rom->pcfg, PINCTRL_STATE_DEFAULT);
1046 if (ret) {
1047 return ret;
1048 }
1049 #endif
1050
1051 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
1052 if (rom->pcie) {
1053 struct pcie_bar mbar;
1054
1055 if (rom->pcie->bdf == PCIE_BDF_NONE) {
1056 return -EINVAL;
1057 }
1058
1059 pcie_probe_mbar(rom->pcie->bdf, 0, &mbar);
1060 pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
1061
1062 device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr,
1063 mbar.size, K_MEM_CACHE_NONE);
1064
1065 pcie_set_cmd(rom->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true);
1066
1067 #ifdef CONFIG_I2C_DW_LPSS_DMA
1068 uintptr_t base;
1069
1070 base = DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET;
1071 dma_intel_lpss_set_base(rom->dma_dev, base);
1072 dma_intel_lpss_setup(rom->dma_dev);
1073
1074 /* Assign physical & virtual address to dma instance */
1075 dw->phy_addr = mbar.phys_addr;
1076 dw->base_addr = (uint32_t)(DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET);
1077 sys_write32((uint32_t)dw->phy_addr,
1078 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW);
1079 sys_write32((uint32_t)(dw->phy_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT),
1080 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI);
1081 LOG_DBG("i2c instance physical addr: [0x%lx], virtual addr: [0x%lx]",
1082 dw->phy_addr, dw->base_addr);
1083 #endif
1084 } else
1085 #endif
1086 {
1087 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
1088 }
1089
1090 k_sem_init(&dw->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1091 k_mutex_init(&dw->bus_mutex);
1092
1093 uint32_t reg_base = get_regs(dev);
1094
1095 clear_bit_enable_en(reg_base);
1096
1097 /* verify that we have a valid DesignWare register first */
1098 if (read_comp_type(reg_base) != I2C_DW_MAGIC_KEY) {
1099 LOG_DBG("I2C: DesignWare magic key not found, check base "
1100 "address. Stopping initialization");
1101 return -EIO;
1102 }
1103
1104 /*
1105 * grab the default value on initialization. This should be set to the
1106 * IC_MAX_SPEED_MODE in the hardware. If it does support high speed we
1107 * can move provide support for it
1108 */
1109 ic_con.raw = read_con(reg_base);
1110 if (ic_con.bits.speed == I2C_DW_SPEED_HIGH) {
1111 LOG_DBG("I2C: high speed supported");
1112 dw->support_hs_mode = true;
1113 } else {
1114 LOG_DBG("I2C: high speed NOT supported");
1115 dw->support_hs_mode = false;
1116 }
1117
1118 rom->config_func(dev);
1119
1120 dw->app_config = I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(rom->bitrate);
1121
1122 if (i2c_dw_runtime_configure(dev, dw->app_config) != 0) {
1123 LOG_DBG("I2C: Cannot set default configuration");
1124 return -EIO;
1125 }
1126
1127 dw->state = I2C_DW_STATE_READY;
1128
1129 return ret;
1130 }
1131
1132 #if defined(CONFIG_PINCTRL)
1133 #define PINCTRL_DW_DEFINE(n) PINCTRL_DT_INST_DEFINE(n)
1134 #define PINCTRL_DW_CONFIG(n) .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
1135 #else
1136 #define PINCTRL_DW_DEFINE(n)
1137 #define PINCTRL_DW_CONFIG(n)
1138 #endif
1139
1140 #if defined(CONFIG_RESET)
1141 #define RESET_DW_CONFIG(n) \
1142 IF_ENABLED(DT_INST_NODE_HAS_PROP(0, resets), \
1143 (.reset = RESET_DT_SPEC_INST_GET(n),))
1144 #else
1145 #define RESET_DW_CONFIG(n)
1146 #endif
1147
1148 #define I2C_DW_INIT_PCIE0(n)
1149 #define I2C_DW_INIT_PCIE1(n) DEVICE_PCIE_INST_INIT(n, pcie),
1150 #define I2C_DW_INIT_PCIE(n) \
1151 _CONCAT(I2C_DW_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1152
1153 #define I2C_DEFINE_PCIE0(n)
1154 #define I2C_DEFINE_PCIE1(n) DEVICE_PCIE_INST_DECLARE(n)
1155 #define I2C_PCIE_DEFINE(n) \
1156 _CONCAT(I2C_DEFINE_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1157
1158 #define I2C_DW_IRQ_FLAGS_SENSE0(n) 0
1159 #define I2C_DW_IRQ_FLAGS_SENSE1(n) DT_INST_IRQ(n, sense)
1160 #define I2C_DW_IRQ_FLAGS(n) \
1161 _CONCAT(I2C_DW_IRQ_FLAGS_SENSE, DT_INST_IRQ_HAS_CELL(n, sense))(n)
1162
1163 /* not PCI(e) */
1164 #define I2C_DW_IRQ_CONFIG_PCIE0(n) \
1165 static void i2c_config_##n(const struct device *port) \
1166 { \
1167 ARG_UNUSED(port); \
1168 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
1169 i2c_dw_isr, DEVICE_DT_INST_GET(n), \
1170 I2C_DW_IRQ_FLAGS(n)); \
1171 irq_enable(DT_INST_IRQN(n)); \
1172 }
1173
1174 /* PCI(e) with auto IRQ detection */
1175 #define I2C_DW_IRQ_CONFIG_PCIE1(n) \
1176 static void i2c_config_##n(const struct device *port) \
1177 { \
1178 BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
1179 "Only runtime IRQ configuration is supported"); \
1180 BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
1181 "DW I2C PCI needs CONFIG_DYNAMIC_INTERRUPTS"); \
1182 const struct i2c_dw_rom_config * const dev_cfg = port->config;\
1183 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1184 if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
1185 return; \
1186 } \
1187 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
1188 DT_INST_IRQ(n, priority), \
1189 (void (*)(const void *))i2c_dw_isr, \
1190 DEVICE_DT_INST_GET(n), \
1191 I2C_DW_IRQ_FLAGS(n)); \
1192 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
1193 }
1194
1195 #define I2C_DW_IRQ_CONFIG(n) \
1196 _CONCAT(I2C_DW_IRQ_CONFIG_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1197
1198 #define I2C_CONFIG_REG_INIT_PCIE0(n) DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),
1199 #define I2C_CONFIG_REG_INIT_PCIE1(n)
1200 #define I2C_CONFIG_REG_INIT(n) \
1201 _CONCAT(I2C_CONFIG_REG_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
1202
1203 #define I2C_CONFIG_DMA_INIT(n) \
1204 COND_CODE_1(CONFIG_I2C_DW_LPSS_DMA, \
1205 (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
1206 (.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(n, 0)),), \
1207 ())), ())
1208
1209 #define I2C_DEVICE_INIT_DW(n) \
1210 PINCTRL_DW_DEFINE(n); \
1211 I2C_PCIE_DEFINE(n); \
1212 static void i2c_config_##n(const struct device *port); \
1213 static const struct i2c_dw_rom_config i2c_config_dw_##n = { \
1214 I2C_CONFIG_REG_INIT(n) \
1215 .config_func = i2c_config_##n, \
1216 .bitrate = DT_INST_PROP(n, clock_frequency), \
1217 RESET_DW_CONFIG(n) \
1218 PINCTRL_DW_CONFIG(n) \
1219 I2C_DW_INIT_PCIE(n) \
1220 I2C_CONFIG_DMA_INIT(n) \
1221 }; \
1222 static struct i2c_dw_dev_config i2c_##n##_runtime; \
1223 I2C_DEVICE_DT_INST_DEFINE(n, i2c_dw_initialize, NULL, \
1224 &i2c_##n##_runtime, &i2c_config_dw_##n, \
1225 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
1226 &funcs); \
1227 I2C_DW_IRQ_CONFIG(n)
1228
1229 DT_INST_FOREACH_STATUS_OKAY(I2C_DEVICE_INIT_DW)
1230
