1 /*
2 * Copyright (c) 2022 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_enhance_i2c
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/pm/policy.h>
15 #include <errno.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/sys/util.h>
19
20 #include <zephyr/logging/log.h>
21 LOG_MODULE_REGISTER(i2c_ite_enhance, CONFIG_I2C_LOG_LEVEL);
22
23 #include "i2c-priv.h"
24
25 /* Start smbus session from idle state */
26 #define I2C_MSG_START BIT(5)
27
28 #define I2C_LINE_SCL_HIGH BIT(0)
29 #define I2C_LINE_SDA_HIGH BIT(1)
30 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
31
32 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
33 /* Reserved 5 bytes for ID and CMD_x. */
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
35
36 /* Repeat Start. */
37 #define I2C_CQ_CMD_L_RS BIT(7)
38 /*
39 * R/W (Read/ Write) decides the I2C read or write direction.
40 * 1: read, 0: write
41 */
42 #define I2C_CQ_CMD_L_RW BIT(6)
43 /* P (STOP) is the I2C STOP condition. */
44 #define I2C_CQ_CMD_L_P BIT(5)
45 /* E (End) is this device end flag. */
46 #define I2C_CQ_CMD_L_E BIT(4)
47 /* LA (Last ACK) is Last ACK in master receiver. */
48 #define I2C_CQ_CMD_L_LA BIT(3)
49 /* bit[2:0] are number of transfer out or receive data which depends on R/W. */
50 #define I2C_CQ_CMD_L_NUM_BIT_2_0 GENMASK(2, 0)
51
52 struct i2c_cq_packet {
53 uint8_t id;
54 uint8_t cmd_l;
55 uint8_t cmd_h;
56 uint8_t wdata[0];
57 };
58 #endif /* CONFIG_I2C_IT8XXX2_CQ_MODE */
59
60 struct i2c_enhance_config {
61 void (*irq_config_func)(void);
62 uint32_t bitrate;
63 uint8_t *base;
64 uint8_t i2c_irq_base;
65 uint8_t port;
66 uint8_t channel_switch_sel;
67 /* SCL GPIO cells */
68 struct gpio_dt_spec scl_gpios;
69 /* SDA GPIO cells */
70 struct gpio_dt_spec sda_gpios;
71 /* I2C alternate configuration */
72 const struct pinctrl_dev_config *pcfg;
73 uint8_t prescale_scl_low;
74 uint8_t data_hold_time;
75 uint32_t clock_gate_offset;
76 bool target_enable;
77 bool target_pio_mode;
78 bool push_pull_recovery;
79 };
80
81 enum i2c_pin_fun {
82 SCL = 0,
83 SDA,
84 };
85
86 enum i2c_ch_status {
87 I2C_CH_NORMAL = 0,
88 I2C_CH_REPEAT_START,
89 I2C_CH_WAIT_READ,
90 I2C_CH_WAIT_NEXT_XFER,
91 };
92
93 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
94 struct i2c_host_cq_buffer {
95 /* Command queue tx payload. */
96 uint8_t i2c_cq_mode_tx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
97 /* Command queue rx payload. */
98 uint8_t i2c_cq_mode_rx_dlm[CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
99 };
100 #endif
101 #ifdef CONFIG_I2C_TARGET
102 /*
103 * When accessing data exceeds the maximum buffer, the actual reload address
104 * is one byte more than the maximum buffer size. Therefore, it is necessary to
105 * have a buffer in place to prevent overwriting other memory.
106 */
107 #define PROTECT_MEM_BUF 4
108 struct i2c_target_dma_buffer {
109 /* Target mode DMA output buffer. */
110 uint8_t __aligned(4)
111 out_buffer[CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE + PROTECT_MEM_BUF];
112 /* Target mode DMA input buffer. */
113 uint8_t __aligned(4)
114 in_buffer[CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE + PROTECT_MEM_BUF];
115 };
116 #endif
117
118 struct i2c_enhance_data {
119 enum i2c_ch_status i2ccs;
120 struct i2c_msg *active_msg;
121 struct k_mutex mutex;
122 struct k_sem device_sync_sem;
123 /* Index into output data */
124 size_t widx;
125 /* Index into input data */
126 size_t ridx;
127 /* operation freq of i2c */
128 uint32_t bus_freq;
129 /* Error code, if any */
130 uint32_t err;
131 /* address of device */
132 uint16_t addr_16bit;
133 /* wait for stop bit interrupt */
134 uint8_t stop;
135 /* Number of messages. */
136 uint8_t num_msgs;
137 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
138 /* Store command queue mode messages. */
139 struct i2c_msg *cq_msgs;
140 #endif
141 #ifdef CONFIG_I2C_TARGET
142 struct i2c_target_config *target_cfg;
143 uint32_t buffer_size;
144 int target_nack;
145 bool target_attached;
146 #endif
147 union {
148 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
149 struct i2c_host_cq_buffer host_buffer;
150 #endif
151 #ifdef CONFIG_I2C_TARGET
152 struct i2c_target_dma_buffer target_buffer;
153 #endif
154 };
155 };
156
157 enum enhanced_i2c_transfer_direct {
158 TX_DIRECT,
159 RX_DIRECT,
160 };
161
162 enum enhanced_i2c_ctl {
163 /* Hardware reset */
164 E_HW_RST = 0x01,
165 /* Stop */
166 E_STOP = 0x02,
167 /* Start & Repeat start */
168 E_START = 0x04,
169 /* Acknowledge */
170 E_ACK = 0x08,
171 /* State reset */
172 E_STS_RST = 0x10,
173 /* Mode select */
174 E_MODE_SEL = 0x20,
175 /* I2C interrupt enable */
176 E_INT_EN = 0x40,
177 /* 0 : Standard mode , 1 : Receive mode */
178 E_RX_MODE = 0x80,
179 /* State reset and hardware reset */
180 E_STS_AND_HW_RST = (E_STS_RST | E_HW_RST),
181 /* Generate start condition and transmit slave address */
182 E_START_ID = (E_INT_EN | E_MODE_SEL | E_ACK | E_START | E_HW_RST),
183 /* Generate stop condition */
184 E_FINISH = (E_INT_EN | E_MODE_SEL | E_ACK | E_STOP | E_HW_RST),
185 /* Start with command queue mode */
186 E_START_CQ = (E_INT_EN | E_MODE_SEL | E_ACK | E_START),
187 };
188
189 enum enhanced_i2c_host_status {
190 /* ACK receive */
191 E_HOSTA_ACK = 0x01,
192 /* Interrupt pending */
193 E_HOSTA_INTP = 0x02,
194 /* Read/Write */
195 E_HOSTA_RW = 0x04,
196 /* Time out error */
197 E_HOSTA_TMOE = 0x08,
198 /* Arbitration lost */
199 E_HOSTA_ARB = 0x10,
200 /* Bus busy */
201 E_HOSTA_BB = 0x20,
202 /* Address match */
203 E_HOSTA_AM = 0x40,
204 /* Byte done status */
205 E_HOSTA_BDS = 0x80,
206 /* time out or lost arbitration */
207 E_HOSTA_ANY_ERROR = (E_HOSTA_TMOE | E_HOSTA_ARB),
208 /* Byte transfer done and ACK receive */
209 E_HOSTA_BDS_AND_ACK = (E_HOSTA_BDS | E_HOSTA_ACK),
210 };
211
212 enum i2c_reset_cause {
213 I2C_RC_NO_IDLE_FOR_START = 1,
214 I2C_RC_TIMEOUT,
215 };
216
217 #ifdef CONFIG_I2C_TARGET
218 enum enhanced_i2c_target_status {
219 /* Time out error */
220 E_TARGET_TMOE = 0x08,
221 /* Arbitration lost */
222 E_TARGET_ARB = 0x10,
223 /* Time out or lost arbitration */
224 E_TARGET_ANY_ERROR = (E_TARGET_TMOE | E_TARGET_ARB),
225 };
226 #endif
227
i2c_parsing_return_value(const struct device * dev)228 static int i2c_parsing_return_value(const struct device *dev)
229 {
230 struct i2c_enhance_data *data = dev->data;
231
232 if (!data->err) {
233 return 0;
234 }
235
236 /* Connection timed out */
237 if (data->err == ETIMEDOUT) {
238 return -ETIMEDOUT;
239 }
240
241 /* The device does not respond ACK */
242 if (data->err == E_HOSTA_ACK) {
243 return -ENXIO;
244 } else {
245 return -EIO;
246 }
247 }
248
i2c_get_line_levels(const struct device * dev)249 static int i2c_get_line_levels(const struct device *dev)
250 {
251 const struct i2c_enhance_config *config = dev->config;
252 uint8_t *base = config->base;
253 int pin_sts = 0;
254
255 if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SCL_IN) {
256 pin_sts |= I2C_LINE_SCL_HIGH;
257 }
258
259 if (IT8XXX2_I2C_TOS(base) & IT8XXX2_I2C_SDA_IN) {
260 pin_sts |= I2C_LINE_SDA_HIGH;
261 }
262
263 return pin_sts;
264 }
265
i2c_is_busy(const struct device * dev)266 static int i2c_is_busy(const struct device *dev)
267 {
268 const struct i2c_enhance_config *config = dev->config;
269 uint8_t *base = config->base;
270
271 return (IT8XXX2_I2C_STR(base) & E_HOSTA_BB);
272 }
273
i2c_bus_not_available(const struct device * dev)274 static int i2c_bus_not_available(const struct device *dev)
275 {
276 if (i2c_is_busy(dev) ||
277 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
278 return -EIO;
279 }
280
281 return 0;
282 }
283
i2c_reset(const struct device * dev)284 static void i2c_reset(const struct device *dev)
285 {
286 const struct i2c_enhance_config *config = dev->config;
287 uint8_t *base = config->base;
288
289 /* State reset and hardware reset */
290 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
291 }
292
293 /* Set clock frequency for i2c port D, E , or F */
i2c_enhanced_port_set_frequency(const struct device * dev,int freq_hz)294 static void i2c_enhanced_port_set_frequency(const struct device *dev,
295 int freq_hz)
296 {
297 const struct i2c_enhance_config *config = dev->config;
298 uint32_t clk_div, psr, pll_clock, psr_h, psr_l;
299 uint8_t *base = config->base;
300 uint8_t prescale_scl = config->prescale_scl_low;
301
302 pll_clock = chip_get_pll_freq();
303 /*
304 * Let psr(Prescale) = IT8XXX2_I2C_PSR(p_ch)
305 * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle
306 * SMBus clock = pll_clock / clk_div
307 * SMBus clock cycle = 1 / SMBus clock
308 * 1 SCL cycle = 1 / freq
309 * 1 / freq = 2 x (psr + 2) x (1 / (pll_clock / clk_div))
310 * psr = ((pll_clock / clk_div) x (1 / freq) x (1 / 2)) - 2
311 */
312 if (freq_hz) {
313 /* Get SMBus clock divide value */
314 clk_div = (IT8XXX2_ECPM_SCDCR2 & 0x0F) + 1U;
315 /* Calculate PSR value */
316 psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U;
317 /* Set psr value under 0xFD */
318 if (psr > 0xFD) {
319 psr = 0xFD;
320 }
321
322 /* Adjust SCL low period prescale */
323 psr_l = psr + prescale_scl;
324 if (psr_l > 0xFD) {
325 psr_l = 0xFD;
326 LOG_WRN("(psr + prescale_scl) can not be greater than 0xfd.");
327 }
328
329 /*
330 * Adjust SCL high period prescale
331 * The property setting prescale_scl must be less than psr and
332 * the minimum value of psr_h is 2.
333 */
334 if (psr > (prescale_scl + 2)) {
335 psr_h = psr - prescale_scl;
336 } else {
337 psr_h = 2;
338 LOG_WRN("prescale_scl_low should be less than (psr - 2).");
339 }
340
341 /* Set I2C Speed for SCL low period. */
342 IT8XXX2_I2C_PSR(base) = psr_l & 0xFF;
343 /* Set I2C Speed for SCL high period. */
344 IT8XXX2_I2C_HSPR(base) = psr_h & 0xFF;
345 }
346
347 }
348
i2c_enhance_configure(const struct device * dev,uint32_t dev_config_raw)349 static int i2c_enhance_configure(const struct device *dev,
350 uint32_t dev_config_raw)
351 {
352 const struct i2c_enhance_config *config = dev->config;
353 struct i2c_enhance_data *const data = dev->data;
354
355 if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
356 return -EINVAL;
357 }
358
359 if (I2C_ADDR_10_BITS & dev_config_raw) {
360 return -EINVAL;
361 }
362
363 data->bus_freq = I2C_SPEED_GET(dev_config_raw);
364
365 i2c_enhanced_port_set_frequency(dev, config->bitrate);
366
367 return 0;
368 }
369
i2c_enhance_get_config(const struct device * dev,uint32_t * dev_config)370 static int i2c_enhance_get_config(const struct device *dev, uint32_t *dev_config)
371 {
372 struct i2c_enhance_data *const data = dev->data;
373 uint32_t speed;
374
375 if (!data->bus_freq) {
376 LOG_ERR("The bus frequency is not initially configured.");
377 return -EIO;
378 }
379
380 switch (data->bus_freq) {
381 case I2C_SPEED_DT:
382 case I2C_SPEED_STANDARD:
383 case I2C_SPEED_FAST:
384 case I2C_SPEED_FAST_PLUS:
385 speed = I2C_SPEED_SET(data->bus_freq);
386 break;
387 default:
388 return -ERANGE;
389 }
390
391 *dev_config = (I2C_MODE_CONTROLLER | speed);
392
393 return 0;
394 }
395
enhanced_i2c_error(const struct device * dev)396 static int enhanced_i2c_error(const struct device *dev)
397 {
398 struct i2c_enhance_data *data = dev->data;
399 const struct i2c_enhance_config *config = dev->config;
400 uint8_t *base = config->base;
401 uint32_t i2c_str = IT8XXX2_I2C_STR(base);
402
403 if (i2c_str & E_HOSTA_ANY_ERROR) {
404 data->err = i2c_str & E_HOSTA_ANY_ERROR;
405 /* device does not respond ACK */
406 } else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
407 if (IT8XXX2_I2C_CTR(base) & E_ACK) {
408 data->err = E_HOSTA_ACK;
409 /* STOP */
410 IT8XXX2_I2C_CTR(base) = E_FINISH;
411 }
412 }
413
414 return data->err;
415 }
416
enhanced_i2c_start(const struct device * dev)417 static void enhanced_i2c_start(const struct device *dev)
418 {
419 const struct i2c_enhance_config *config = dev->config;
420 uint8_t *base = config->base;
421
422 /* reset i2c port */
423 i2c_reset(dev);
424 /* Set i2c frequency */
425 i2c_enhanced_port_set_frequency(dev, config->bitrate);
426 /*
427 * Set time out register.
428 * I2C D/E/F clock/data low timeout.
429 */
430 IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
431 /* bit1: Enable enhanced i2c module */
432 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN;
433 }
434
i2c_pio_trans_data(const struct device * dev,enum enhanced_i2c_transfer_direct direct,uint16_t trans_data,int first_byte)435 static void i2c_pio_trans_data(const struct device *dev,
436 enum enhanced_i2c_transfer_direct direct,
437 uint16_t trans_data, int first_byte)
438 {
439 struct i2c_enhance_data *data = dev->data;
440 const struct i2c_enhance_config *config = dev->config;
441 uint8_t *base = config->base;
442 uint32_t nack = 0;
443
444 if (first_byte) {
445 /* First byte must be slave address. */
446 IT8XXX2_I2C_DTR(base) = trans_data |
447 (direct == RX_DIRECT ? BIT(0) : 0);
448 /* start or repeat start signal. */
449 IT8XXX2_I2C_CTR(base) = E_START_ID;
450 } else {
451 if (direct == TX_DIRECT) {
452 /* Transmit data */
453 IT8XXX2_I2C_DTR(base) = (uint8_t)trans_data;
454 } else {
455 /*
456 * Receive data.
457 * Last byte should be NACK in the end of read cycle
458 */
459 if (((data->ridx + 1) == data->active_msg->len) &&
460 (data->active_msg->flags & I2C_MSG_STOP)) {
461 nack = 1;
462 }
463 }
464 /* Set hardware reset to start next transmission */
465 IT8XXX2_I2C_CTR(base) = E_INT_EN | E_MODE_SEL |
466 E_HW_RST | (nack ? 0 : E_ACK);
467 }
468 }
469
enhanced_i2c_tran_read(const struct device * dev)470 static int enhanced_i2c_tran_read(const struct device *dev)
471 {
472 struct i2c_enhance_data *data = dev->data;
473 const struct i2c_enhance_config *config = dev->config;
474 uint8_t *base = config->base;
475 uint8_t in_data = 0;
476
477 if (data->active_msg->flags & I2C_MSG_START) {
478 /* clear start flag */
479 data->active_msg->flags &= ~I2C_MSG_START;
480 enhanced_i2c_start(dev);
481 /* Direct read */
482 data->i2ccs = I2C_CH_WAIT_READ;
483 /* Send ID */
484 i2c_pio_trans_data(dev, RX_DIRECT, data->addr_16bit << 1, 1);
485 } else {
486 if (data->i2ccs) {
487 if (data->i2ccs == I2C_CH_WAIT_READ) {
488 data->i2ccs = I2C_CH_NORMAL;
489 /* Receive data */
490 i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
491
492 /* data->active_msg->flags == I2C_MSG_RESTART */
493 } else {
494 /* Write to read */
495 data->i2ccs = I2C_CH_WAIT_READ;
496 /* Send ID */
497 i2c_pio_trans_data(dev, RX_DIRECT,
498 data->addr_16bit << 1, 1);
499 }
500 } else {
501 if (data->ridx < data->active_msg->len) {
502 /* read data */
503 *(data->active_msg->buf++) = IT8XXX2_I2C_DRR(base);
504 data->ridx++;
505 /* done */
506 if (data->ridx == data->active_msg->len) {
507 data->active_msg->len = 0;
508 if (data->active_msg->flags & I2C_MSG_STOP) {
509 data->i2ccs = I2C_CH_NORMAL;
510 IT8XXX2_I2C_CTR(base) = E_FINISH;
511 /* wait for stop bit interrupt */
512 data->stop = 1;
513 return 1;
514 }
515 /* End the transaction */
516 data->i2ccs = I2C_CH_WAIT_READ;
517 return 0;
518 }
519 /* read next byte */
520 i2c_pio_trans_data(dev, RX_DIRECT, in_data, 0);
521 }
522 }
523 }
524 return 1;
525 }
526
enhanced_i2c_tran_write(const struct device * dev)527 static int enhanced_i2c_tran_write(const struct device *dev)
528 {
529 struct i2c_enhance_data *data = dev->data;
530 const struct i2c_enhance_config *config = dev->config;
531 uint8_t *base = config->base;
532 uint8_t out_data;
533
534 if (data->active_msg->flags & I2C_MSG_START) {
535 /* Clear start bit */
536 data->active_msg->flags &= ~I2C_MSG_START;
537 enhanced_i2c_start(dev);
538 /* Send ID */
539 i2c_pio_trans_data(dev, TX_DIRECT, data->addr_16bit << 1, 1);
540 } else {
541 /* Host has completed the transmission of a byte */
542 if (data->widx < data->active_msg->len) {
543 out_data = *(data->active_msg->buf++);
544 data->widx++;
545
546 /* Send Byte */
547 i2c_pio_trans_data(dev, TX_DIRECT, out_data, 0);
548 if (data->i2ccs == I2C_CH_WAIT_NEXT_XFER) {
549 data->i2ccs = I2C_CH_NORMAL;
550 }
551 } else {
552 /* done */
553 data->active_msg->len = 0;
554 if (data->active_msg->flags & I2C_MSG_STOP) {
555 IT8XXX2_I2C_CTR(base) = E_FINISH;
556 /* wait for stop bit interrupt */
557 data->stop = 1;
558 } else {
559 /* Direct write with direct read */
560 data->i2ccs = I2C_CH_WAIT_NEXT_XFER;
561 return 0;
562 }
563 }
564 }
565 return 1;
566 }
567
i2c_transaction(const struct device * dev)568 static int i2c_transaction(const struct device *dev)
569 {
570 struct i2c_enhance_data *data = dev->data;
571 const struct i2c_enhance_config *config = dev->config;
572 uint8_t *base = config->base;
573
574 /* no error */
575 if (!(enhanced_i2c_error(dev))) {
576 if (!data->stop) {
577 /*
578 * The return value indicates if there is more data
579 * to be read or written. If the return value = 1,
580 * it means that the interrupt cannot be disable and
581 * continue to transmit data.
582 */
583 if (data->active_msg->flags & I2C_MSG_READ) {
584 return enhanced_i2c_tran_read(dev);
585 } else {
586 return enhanced_i2c_tran_write(dev);
587 }
588 }
589 }
590 /* reset i2c port */
591 i2c_reset(dev);
592 IT8XXX2_I2C_CTR1(base) = 0;
593
594 data->stop = 0;
595 /* done doing work */
596 return 0;
597 }
598
i2c_enhance_pio_transfer(const struct device * dev,struct i2c_msg * msgs)599 static int i2c_enhance_pio_transfer(const struct device *dev,
600 struct i2c_msg *msgs)
601 {
602 struct i2c_enhance_data *data = dev->data;
603 const struct i2c_enhance_config *config = dev->config;
604 int res;
605
606 if (data->i2ccs == I2C_CH_NORMAL) {
607 struct i2c_msg *start_msg = &msgs[0];
608
609 start_msg->flags |= I2C_MSG_START;
610 }
611
612 for (int i = 0; i < data->num_msgs; i++) {
613
614 data->widx = 0;
615 data->ridx = 0;
616 data->err = 0;
617 data->active_msg = &msgs[i];
618
619 /*
620 * Start transaction.
621 * The return value indicates if the initial configuration
622 * of I2C transaction for read or write has been completed.
623 */
624 if (i2c_transaction(dev)) {
625 /* Enable I2C interrupt. */
626 irq_enable(config->i2c_irq_base);
627 }
628 /* Wait for the transfer to complete */
629 /* TODO: the timeout should be adjustable */
630 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
631 /*
632 * The irq will be enabled at the condition of start or
633 * repeat start of I2C. If timeout occurs without being
634 * wake up during suspend(ex: interrupt is not fired),
635 * the irq should be disabled immediately.
636 */
637 irq_disable(config->i2c_irq_base);
638 /*
639 * The transaction is dropped on any error(timeout, NACK, fail,
640 * bus error, device error).
641 */
642 if (data->err) {
643 break;
644 }
645
646 if (res != 0) {
647 data->err = ETIMEDOUT;
648 /* reset i2c port */
649 i2c_reset(dev);
650 LOG_ERR("I2C ch%d:0x%X reset cause %d",
651 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
652 /* If this message is sent fail, drop the transaction. */
653 break;
654 }
655 }
656
657 /* reset i2c channel status */
658 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
659 data->i2ccs = I2C_CH_NORMAL;
660 }
661
662 return data->err;
663 }
664
665 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
enhanced_i2c_set_cmd_addr_regs(const struct device * dev)666 static void enhanced_i2c_set_cmd_addr_regs(const struct device *dev)
667 {
668 const struct i2c_enhance_config *config = dev->config;
669 struct i2c_enhance_data *data = dev->data;
670 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
671 uint32_t dlm_base;
672 uint8_t *base = config->base;
673
674 /* Set "Address Register" to store the I2C data. */
675 dlm_base = (uint32_t)host_buffer->i2c_cq_mode_rx_dlm & 0xffffff;
676 IT8XXX2_I2C_RAMH2A(base) = (dlm_base >> 16) & 0xff;
677 IT8XXX2_I2C_RAMHA(base) = (dlm_base >> 8) & 0xff;
678 IT8XXX2_I2C_RAMLA(base) = dlm_base & 0xff;
679
680 /* Set "Command Address Register" to get commands. */
681 dlm_base = (uint32_t)host_buffer->i2c_cq_mode_tx_dlm & 0xffffff;
682 IT8XXX2_I2C_CMD_ADDH2(base) = (dlm_base >> 16) & 0xff;
683 IT8XXX2_I2C_CMD_ADDH(base) = (dlm_base >> 8) & 0xff;
684 IT8XXX2_I2C_CMD_ADDL(base) = dlm_base & 0xff;
685 }
686
enhanced_i2c_cq_write(const struct device * dev)687 static void enhanced_i2c_cq_write(const struct device *dev)
688 {
689 struct i2c_enhance_data *data = dev->data;
690 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
691 struct i2c_cq_packet *i2c_cq_pckt;
692 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
693 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
694
695 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
696 /* Set commands in RAM. */
697 i2c_cq_pckt->id = data->addr_16bit << 1;
698 i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
699 i2c_cq_pckt->cmd_h = num_bit_10_3;
700 for (int i = 0; i < data->cq_msgs[0].len; i++) {
701 i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i];
702 }
703 }
704
enhanced_i2c_cq_read(const struct device * dev)705 static void enhanced_i2c_cq_read(const struct device *dev)
706 {
707 struct i2c_enhance_data *data = dev->data;
708 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
709 struct i2c_cq_packet *i2c_cq_pckt;
710 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
711 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
712
713 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
714 /* Set commands in RAM. */
715 i2c_cq_pckt->id = data->addr_16bit << 1;
716 i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P |
717 I2C_CQ_CMD_L_E | num_bit_2_0;
718 i2c_cq_pckt->cmd_h = num_bit_10_3;
719 }
720
enhanced_i2c_cq_write_to_read(const struct device * dev)721 static void enhanced_i2c_cq_write_to_read(const struct device *dev)
722 {
723 struct i2c_enhance_data *data = dev->data;
724 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
725 struct i2c_cq_packet *i2c_cq_pckt;
726 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
727 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff;
728 int i;
729
730 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm;
731 /* Set commands in RAM. (command byte for write) */
732 i2c_cq_pckt->id = data->addr_16bit << 1;
733 i2c_cq_pckt->cmd_l = num_bit_2_0;
734 i2c_cq_pckt->cmd_h = num_bit_10_3;
735 for (i = 0; i < data->cq_msgs[0].len; i++) {
736 i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i];
737 }
738
739 /* Set commands in RAM. (command byte for read) */
740 num_bit_2_0 = (data->cq_msgs[1].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
741 num_bit_10_3 = ((data->cq_msgs[1].len - 1) >> 3) & 0xff;
742 i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW |
743 I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
744 i2c_cq_pckt->wdata[i] = num_bit_10_3;
745 }
746
enhanced_i2c_cq_isr(const struct device * dev)747 static int enhanced_i2c_cq_isr(const struct device *dev)
748 {
749 struct i2c_enhance_data *data = dev->data;
750 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer;
751 const struct i2c_enhance_config *config = dev->config;
752 uint8_t *base = config->base;
753
754 /* Device 1 finish IRQ. */
755 if (IT8XXX2_I2C_FST(base) & IT8XXX2_I2C_FST_DEV1_IRQ) {
756 uint8_t msgs_idx = data->num_msgs - 1;
757
758 /* Get data if this is a read transaction. */
759 if (data->cq_msgs[msgs_idx].flags & I2C_MSG_READ) {
760 for (int i = 0; i < data->cq_msgs[msgs_idx].len; i++) {
761 data->cq_msgs[msgs_idx].buf[i] =
762 host_buffer->i2c_cq_mode_rx_dlm[i];
763 }
764 }
765 } else {
766 /* Device 1 error have occurred. eg. nack, timeout... */
767 if (IT8XXX2_I2C_NST(base) & IT8XXX2_I2C_NST_ID_NACK) {
768 data->err = E_HOSTA_ACK;
769 } else {
770 data->err = IT8XXX2_I2C_STR(base) &
771 E_HOSTA_ANY_ERROR;
772 }
773 }
774 /* Reset bus. */
775 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
776 IT8XXX2_I2C_CTR1(base) = 0;
777
778 return 0;
779 }
780
enhanced_i2c_cmd_queue_trans(const struct device * dev)781 static int enhanced_i2c_cmd_queue_trans(const struct device *dev)
782 {
783 struct i2c_enhance_data *data = dev->data;
784 const struct i2c_enhance_config *config = dev->config;
785 uint8_t *base = config->base;
786
787 /* State reset and hardware reset. */
788 IT8XXX2_I2C_CTR(base) = E_STS_AND_HW_RST;
789 /* Set "PSR" registers to decide the i2c speed. */
790 i2c_enhanced_port_set_frequency(dev, config->bitrate);
791 /* Set time out register. port D, E, or F clock/data low timeout. */
792 IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
793
794 if (data->num_msgs == 2) {
795 /* I2C write to read of command queue mode. */
796 enhanced_i2c_cq_write_to_read(dev);
797 } else {
798 /* I2C read of command queue mode. */
799 if (data->cq_msgs[0].flags & I2C_MSG_READ) {
800 enhanced_i2c_cq_read(dev);
801 /* I2C write of command queue mode. */
802 } else {
803 enhanced_i2c_cq_write(dev);
804 }
805 }
806
807 /* Enable i2c module with command queue mode. */
808 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN | IT8XXX2_I2C_COMQ_EN;
809 /* One shot on device 1. */
810 IT8XXX2_I2C_MODE_SEL(base) = 0;
811 IT8XXX2_I2C_CTR2(base) = 1;
812 /*
813 * The EC processor(CPU) cannot be in the k_cpu_idle() and power
814 * policy during the transactions with the CQ mode(DMA mode).
815 * Otherwise, the EC processor would be clock gated.
816 */
817 chip_block_idle();
818 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
819 /* Start */
820 IT8XXX2_I2C_CTR(base) = E_START_CQ;
821
822 return 1;
823 }
824
i2c_enhance_cq_transfer(const struct device * dev,struct i2c_msg * msgs)825 static int i2c_enhance_cq_transfer(const struct device *dev,
826 struct i2c_msg *msgs)
827 {
828 struct i2c_enhance_data *data = dev->data;
829 const struct i2c_enhance_config *config = dev->config;
830 int res = 0;
831
832 data->err = 0;
833 data->cq_msgs = msgs;
834
835 /* Start transaction */
836 if (enhanced_i2c_cmd_queue_trans(dev)) {
837 /* Enable i2c interrupt */
838 irq_enable(config->i2c_irq_base);
839 }
840 /* Wait for the transfer to complete */
841 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
842
843 irq_disable(config->i2c_irq_base);
844
845 if (res != 0) {
846 data->err = ETIMEDOUT;
847 /* Reset i2c port. */
848 i2c_reset(dev);
849 LOG_ERR("I2C ch%d:0x%X reset cause %d",
850 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
851 }
852
853 /* Permit to enter power policy and idle mode. */
854 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
855 chip_permit_idle();
856
857 return data->err;
858 }
859
cq_mode_allowed(const struct device * dev,struct i2c_msg * msgs)860 static bool cq_mode_allowed(const struct device *dev, struct i2c_msg *msgs)
861 {
862 struct i2c_enhance_data *data = dev->data;
863
864 /*
865 * If the transaction of write or read is divided into two
866 * transfers(not two messages), the command queue mode does
867 * not support.
868 */
869 if (data->i2ccs != I2C_CH_NORMAL) {
870 return false;
871 }
872 /*
873 * When there is only one message, use the command queue transfer
874 * directly.
875 */
876 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP)) {
877 /* Read transfer payload too long, use PIO mode */
878 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
879 (msgs[0].len > CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
880 return false;
881 }
882 /* Write transfer payload too long, use PIO mode */
883 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
884 (msgs[0].len > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE)) {
885 return false;
886 }
887 /*
888 * Write of I2C target address without writing data, used by
889 * cmd_i2c_scan. Use PIO mode.
890 */
891 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
892 (msgs[0].len == 0)) {
893 return false;
894 }
895 return true;
896 }
897 /*
898 * When there are two messages, we need to judge whether or not there
899 * is I2C_MSG_RESTART flag from the second message, and then decide to
900 * do the command queue or PIO mode transfer.
901 */
902 if (data->num_msgs == 2) {
903 /*
904 * The first of two messages must be write.
905 * If the length of write to read transfer is greater than
906 * command queue payload size, there will execute PIO mode.
907 */
908 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
909 (msgs[0].len <= I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE)) {
910 /*
911 * The transfer is i2c_burst_read().
912 *
913 * e.g. msg[0].flags = I2C_MSG_WRITE;
914 * msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
915 * I2C_MSG_STOP;
916 */
917 if ((msgs[1].flags & I2C_MSG_RESTART) &&
918 ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
919 (msgs[1].flags & I2C_MSG_STOP) &&
920 (msgs[1].len <= CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
921 return true;
922 }
923 }
924 }
925
926 return false;
927 }
928 #endif /* CONFIG_I2C_IT8XXX2_CQ_MODE */
929
i2c_enhance_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)930 static int i2c_enhance_transfer(const struct device *dev,
931 struct i2c_msg *msgs,
932 uint8_t num_msgs, uint16_t addr)
933 {
934 struct i2c_enhance_data *data = dev->data;
935 int ret;
936
937 #ifdef CONFIG_I2C_TARGET
938 if (data->target_attached) {
939 LOG_ERR("Device is registered as target");
940 return -EBUSY;
941 }
942 #endif
943 /* Lock mutex of i2c controller */
944 k_mutex_lock(&data->mutex, K_FOREVER);
945
946 data->num_msgs = num_msgs;
947 data->addr_16bit = addr;
948 /*
949 * If the transaction of write to read is divided into two
950 * transfers, the repeat start transfer uses this flag to
951 * exclude checking bus busy.
952 */
953 if (data->i2ccs == I2C_CH_NORMAL) {
954 /* Make sure we're in a good state to start */
955 if (i2c_bus_not_available(dev)) {
956 /* Recovery I2C bus */
957 i2c_recover_bus(dev);
958 /*
959 * After resetting I2C bus, if I2C bus is not available
960 * (No external pull-up), drop the transaction.
961 */
962 if (i2c_bus_not_available(dev)) {
963 /* Unlock mutex of i2c controller */
964 k_mutex_unlock(&data->mutex);
965 return -EIO;
966 }
967 }
968 }
969
970 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
971 if (cq_mode_allowed(dev, msgs)) {
972 data->err = i2c_enhance_cq_transfer(dev, msgs);
973 } else
974 #endif
975 {
976 data->err = i2c_enhance_pio_transfer(dev, msgs);
977 }
978 /* Save return value. */
979 ret = i2c_parsing_return_value(dev);
980 /* Unlock mutex of i2c controller */
981 k_mutex_unlock(&data->mutex);
982
983 return ret;
984 }
985
986 #ifdef CONFIG_I2C_TARGET
target_i2c_isr_dma(const struct device * dev,uint8_t interrupt_status)987 static void target_i2c_isr_dma(const struct device *dev,
988 uint8_t interrupt_status)
989 {
990 struct i2c_enhance_data *data = dev->data;
991 const struct i2c_enhance_config *config = dev->config;
992 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
993 struct i2c_target_dma_buffer *target_buffer = &data->target_buffer;
994 uint8_t *base = config->base;
995
996 /* Byte counter enable */
997 if (interrupt_status & IT8XXX2_I2C_IDW_CLR) {
998 IT8XXX2_I2C_BYTE_CNT_L(base) |=
999 (IT8XXX2_I2C_DMA_ADDR_RELOAD |
1000 IT8XXX2_I2C_BYTE_CNT_ENABLE);
1001 }
1002 /* The number of received data exceeds the byte counter setting */
1003 if (interrupt_status & IT8XXX2_I2C_CNT_HOLD) {
1004 LOG_ERR("The excess data written starts "
1005 "from the memory address:%p",
1006 target_buffer->in_buffer +
1007 CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE);
1008 }
1009 /* Controller to write data */
1010 if (interrupt_status & IT8XXX2_I2C_SLVDATAFLG) {
1011 /* Number of receive data in target mode */
1012 data->buffer_size =
1013 ((IT8XXX2_I2C_SLV_NUM_H(base) << 8) |
1014 IT8XXX2_I2C_SLV_NUM_L(base)) + 1;
1015
1016 /* Write data done callback function */
1017 target_cb->buf_write_received(data->target_cfg,
1018 target_buffer->in_buffer, data->buffer_size);
1019 }
1020 /* Peripheral finish */
1021 if (interrupt_status & IT8XXX2_I2C_P_CLR) {
1022 /* Transfer done callback function */
1023 target_cb->stop(data->target_cfg);
1024 }
1025 /* Controller to read data */
1026 if (interrupt_status & IT8XXX2_I2C_IDR_CLR) {
1027 uint32_t len;
1028 uint8_t *rdata = NULL;
1029
1030 /* Clear byte counter setting */
1031 IT8XXX2_I2C_BYTE_CNT_L(base) &=
1032 ~(IT8XXX2_I2C_DMA_ADDR_RELOAD |
1033 IT8XXX2_I2C_BYTE_CNT_ENABLE);
1034 /* Read data callback function */
1035 target_cb->buf_read_requested(data->target_cfg,
1036 &rdata, &len);
1037
1038 if (len > CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE) {
1039 LOG_ERR("The buffer size exceeds "
1040 "I2C_TARGET_IT8XXX2_MAX_BUF_SIZE: len=%d",
1041 len);
1042 } else {
1043 memcpy(target_buffer->out_buffer, rdata, len);
1044 }
1045 }
1046
1047 /* Write clear the peripheral status */
1048 IT8XXX2_I2C_IRQ_ST(base) = interrupt_status;
1049 }
1050
target_i2c_isr_pio(const struct device * dev,uint8_t interrupt_status,uint8_t target_status)1051 static int target_i2c_isr_pio(const struct device *dev,
1052 uint8_t interrupt_status,
1053 uint8_t target_status)
1054 {
1055 struct i2c_enhance_data *data = dev->data;
1056 const struct i2c_enhance_config *config = dev->config;
1057 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
1058 int ret = 0;
1059 uint8_t *base = config->base;
1060 uint8_t val;
1061
1062 /* Target ID write flag */
1063 if (interrupt_status & IT8XXX2_I2C_IDW_CLR) {
1064 ret = target_cb->write_requested(data->target_cfg);
1065 }
1066 /* Target ID read flag */
1067 else if (interrupt_status & IT8XXX2_I2C_IDR_CLR) {
1068 if (!target_cb->read_requested(data->target_cfg, &val)) {
1069 IT8XXX2_I2C_DTR(base) = val;
1070 }
1071 }
1072 /* Byte transfer done */
1073 else if (target_status & IT8XXX2_I2C_BYTE_DONE) {
1074 /* Read of write */
1075 if (target_status & IT8XXX2_I2C_RW) {
1076 /* Host receiving, target transmitting */
1077 if (!target_cb->read_processed(data->target_cfg, &val)) {
1078 IT8XXX2_I2C_DTR(base) = val;
1079 }
1080 } else {
1081 /* Host transmitting, target receiving */
1082 val = IT8XXX2_I2C_DRR(base);
1083 ret = target_cb->write_received(data->target_cfg, val);
1084 }
1085 }
1086
1087 return ret;
1088 }
1089
target_i2c_isr(const struct device * dev)1090 static void target_i2c_isr(const struct device *dev)
1091 {
1092 struct i2c_enhance_data *data = dev->data;
1093 const struct i2c_enhance_config *config = dev->config;
1094 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
1095 uint8_t *base = config->base;
1096 uint8_t target_status = IT8XXX2_I2C_STR(base);
1097
1098 /* Any error */
1099 if (target_status & E_TARGET_ANY_ERROR) {
1100 /* Hardware reset */
1101 IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
1102 return;
1103 }
1104
1105 /* Interrupt pending */
1106 if (target_status & IT8XXX2_I2C_INT_PEND) {
1107 uint8_t interrupt_status = IT8XXX2_I2C_IRQ_ST(base);
1108
1109 /* Determine whether the transaction uses PIO or DMA mode */
1110 if (config->target_pio_mode) {
1111 if (target_i2c_isr_pio(dev, interrupt_status, target_status) < 0) {
1112 /* NACK */
1113 IT8XXX2_I2C_CTR(base) &= ~IT8XXX2_I2C_ACK;
1114 IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
1115 data->target_nack = 1;
1116 }
1117 /* Peripheral finish */
1118 if (interrupt_status & IT8XXX2_I2C_P_CLR) {
1119 /* Transfer done callback function */
1120 target_cb->stop(data->target_cfg);
1121
1122 if (data->target_nack) {
1123 /* Set acknowledge */
1124 IT8XXX2_I2C_CTR(base) |=
1125 IT8XXX2_I2C_ACK;
1126 data->target_nack = 0;
1127 }
1128 }
1129 /* Write clear the peripheral status */
1130 IT8XXX2_I2C_IRQ_ST(base) = interrupt_status;
1131 /* Hardware reset */
1132 IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
1133 } else {
1134 target_i2c_isr_dma(dev, interrupt_status);
1135 }
1136 }
1137 }
1138 #endif
1139
i2c_enhance_isr(void * arg)1140 static void i2c_enhance_isr(void *arg)
1141 {
1142 struct device *dev = (struct device *)arg;
1143 struct i2c_enhance_data *data = dev->data;
1144 const struct i2c_enhance_config *config = dev->config;
1145
1146 #ifdef CONFIG_I2C_TARGET
1147 if (data->target_attached) {
1148 target_i2c_isr(dev);
1149 } else {
1150 #endif
1151 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
1152 uint8_t *base = config->base;
1153
1154 /* If done doing work, wake up the task waiting for the transfer */
1155 if (IT8XXX2_I2C_CTR1(base) & IT8XXX2_I2C_COMQ_EN) {
1156 if (enhanced_i2c_cq_isr(dev)) {
1157 return;
1158 }
1159 } else
1160 #endif
1161 {
1162 if (i2c_transaction(dev)) {
1163 return;
1164 }
1165 }
1166 irq_disable(config->i2c_irq_base);
1167 k_sem_give(&data->device_sync_sem);
1168 #ifdef CONFIG_I2C_TARGET
1169 }
1170 #endif
1171 }
1172
i2c_enhance_init(const struct device * dev)1173 static int i2c_enhance_init(const struct device *dev)
1174 {
1175 struct i2c_enhance_data *data = dev->data;
1176 const struct i2c_enhance_config *config = dev->config;
1177 uint8_t *base = config->base;
1178 uint8_t data_hold_time = config->data_hold_time;
1179 uint32_t bitrate_cfg;
1180 int error, status;
1181
1182 #ifdef CONFIG_I2C_TARGET
1183 if (!config->target_enable) {
1184 #endif
1185 /* Initialize mutex and semaphore */
1186 k_mutex_init(&data->mutex);
1187 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1188
1189 /* Enable clock to specified peripheral */
1190 volatile uint8_t *reg = (volatile uint8_t *)
1191 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
1192 uint8_t reg_mask = config->clock_gate_offset & 0xff;
1193 *reg &= ~reg_mask;
1194
1195 /* Enable I2C function */
1196 /* Software reset */
1197 IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
1198 IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
1199 /* reset i2c port */
1200 i2c_reset(dev);
1201 /* bit1, Module enable */
1202 IT8XXX2_I2C_CTR1(base) = 0;
1203
1204 #ifdef CONFIG_I2C_IT8XXX2_CQ_MODE
1205 /* Set command address registers. */
1206 enhanced_i2c_set_cmd_addr_regs(dev);
1207 #endif
1208
1209 /* ChannelA-F switch selection of I2C pin */
1210 if (config->port == SMB_CHANNEL_A) {
1211 IT8XXX2_SMB_SMB01CHS = (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(2, 0)) |
1212 config->channel_switch_sel;
1213 } else if (config->port == SMB_CHANNEL_B) {
1214 IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) |
1215 (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(6, 4));
1216 } else if (config->port == SMB_CHANNEL_C) {
1217 IT8XXX2_SMB_SMB23CHS = (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(2, 0)) |
1218 config->channel_switch_sel;
1219 } else if (config->port == I2C_CHANNEL_D) {
1220 IT8XXX2_SMB_SMB23CHS = (config->channel_switch_sel << 4) |
1221 (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(6, 4));
1222 } else if (config->port == I2C_CHANNEL_E) {
1223 IT8XXX2_SMB_SMB45CHS = (IT8XXX2_SMB_SMB45CHS &= ~GENMASK(2, 0)) |
1224 config->channel_switch_sel;
1225 } else if (config->port == I2C_CHANNEL_F) {
1226 IT8XXX2_SMB_SMB45CHS = (config->channel_switch_sel << 4) |
1227 (IT8XXX2_SMB_SMB45CHS &= ~GENMASK(6, 4));
1228 }
1229
1230 /* Set I2C data hold time. */
1231 IT8XXX2_I2C_DHTR(base) = (IT8XXX2_I2C_DHTR(base) & ~GENMASK(2, 0)) |
1232 (data_hold_time - 3);
1233
1234 /* Set clock frequency for I2C ports */
1235 if (config->bitrate == I2C_BITRATE_STANDARD ||
1236 config->bitrate == I2C_BITRATE_FAST ||
1237 config->bitrate == I2C_BITRATE_FAST_PLUS) {
1238 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
1239 } else {
1240 /* Device tree specified speed */
1241 bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
1242 }
1243
1244 error = i2c_enhance_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1245 data->i2ccs = I2C_CH_NORMAL;
1246
1247 if (error) {
1248 LOG_ERR("i2c: failure initializing");
1249 return error;
1250 }
1251 #ifdef CONFIG_I2C_TARGET
1252 }
1253 #endif
1254
1255 /* Set the pin to I2C alternate function. */
1256 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1257 if (status < 0) {
1258 LOG_ERR("Failed to configure I2C pins");
1259 return status;
1260 }
1261
1262
1263 return 0;
1264 }
1265
i2c_enhance_recover_bus(const struct device * dev)1266 static int i2c_enhance_recover_bus(const struct device *dev)
1267 {
1268 const struct i2c_enhance_config *config = dev->config;
1269 int i, status;
1270
1271 /* Output type selection */
1272 gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
1273 /* Set SCL of I2C as GPIO pin */
1274 gpio_pin_configure_dt(&config->scl_gpios, flags);
1275 /* Set SDA of I2C as GPIO pin */
1276 gpio_pin_configure_dt(&config->sda_gpios, flags);
1277
1278 /*
1279 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
1280 * is mainly to ensure that gpio has enough time to go from
1281 * low to high or high to low.
1282 */
1283 /* Pull SCL and SDA pin to high */
1284 gpio_pin_set_dt(&config->scl_gpios, 1);
1285 gpio_pin_set_dt(&config->sda_gpios, 1);
1286 k_msleep(1);
1287
1288 /* Start condition */
1289 gpio_pin_set_dt(&config->sda_gpios, 0);
1290 k_msleep(1);
1291 gpio_pin_set_dt(&config->scl_gpios, 0);
1292 k_msleep(1);
1293
1294 /* 9 cycles of SCL with SDA held high */
1295 for (i = 0; i < 9; i++) {
1296 /* SDA */
1297 gpio_pin_set_dt(&config->sda_gpios, 1);
1298 /* SCL */
1299 gpio_pin_set_dt(&config->scl_gpios, 1);
1300 k_msleep(1);
1301 /* SCL */
1302 gpio_pin_set_dt(&config->scl_gpios, 0);
1303 k_msleep(1);
1304 }
1305 /* SDA */
1306 gpio_pin_set_dt(&config->sda_gpios, 0);
1307 k_msleep(1);
1308
1309 /* Stop condition */
1310 gpio_pin_set_dt(&config->scl_gpios, 1);
1311 k_msleep(1);
1312 gpio_pin_set_dt(&config->sda_gpios, 1);
1313 k_msleep(1);
1314
1315 /* Set GPIO back to I2C alternate function */
1316 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1317 if (status < 0) {
1318 LOG_ERR("Failed to configure I2C pins");
1319 return status;
1320 }
1321
1322 /* reset i2c port */
1323 i2c_reset(dev);
1324 LOG_ERR("I2C ch%d reset cause %d", config->port,
1325 I2C_RC_NO_IDLE_FOR_START);
1326
1327 return 0;
1328 }
1329
1330 #ifdef CONFIG_I2C_TARGET
i2c_enhance_target_register(const struct device * dev,struct i2c_target_config * target_cfg)1331 static int i2c_enhance_target_register(const struct device *dev,
1332 struct i2c_target_config *target_cfg)
1333 {
1334 const struct i2c_enhance_config *config = dev->config;
1335 struct i2c_enhance_data *data = dev->data;
1336 uint8_t *base = config->base;
1337
1338 if (!target_cfg) {
1339 return -EINVAL;
1340 }
1341
1342 if (target_cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) {
1343 return -ENOTSUP;
1344 }
1345
1346 if (data->target_attached) {
1347 return -EBUSY;
1348 }
1349
1350 data->target_cfg = target_cfg;
1351 data->target_attached = true;
1352
1353 /* Software reset */
1354 IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
1355 IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
1356 /* Disable the timeout setting when clock/data are in a low state */
1357 IT8XXX2_I2C_TO_ARB_ST(base) &= ~(IT8XXX2_I2C_SCL_TIMEOUT_EN |
1358 IT8XXX2_I2C_SDA_TIMEOUT_EN);
1359 /* Bit stretching */
1360 IT8XXX2_I2C_TOS(base) |= IT8XXX2_I2C_CLK_STRETCH;
1361 /* Peripheral address(8-bit) */
1362 IT8XXX2_I2C_IDR(base) = target_cfg->address << 1;
1363 /* I2C interrupt enable and set acknowledge */
1364 IT8XXX2_I2C_CTR(base) = IT8XXX2_I2C_INT_EN | IT8XXX2_I2C_HALT |
1365 IT8XXX2_I2C_ACK;
1366 /* Interrupt status write clear */
1367 IT8XXX2_I2C_IRQ_ST(base) = 0xff;
1368
1369 /* I2C target initial configuration of PIO mode */
1370 if (config->target_pio_mode) {
1371 /* Block to enter power policy. */
1372 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1373
1374 /* I2C module enable */
1375 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_MDL_EN;
1376 /* I2C target initial configuration of DMA mode */
1377 } else {
1378 struct i2c_target_dma_buffer *target_buffer = &data->target_buffer;
1379 uint32_t in_data_addr, out_data_addr;
1380 int buf_size = CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE;
1381
1382 /* Clear read and write data buffer of DMA */
1383 memset(target_buffer->in_buffer, 0, buf_size);
1384 memset(target_buffer->out_buffer, 0, buf_size);
1385
1386 in_data_addr = (uint32_t)target_buffer->in_buffer & 0xffffff;
1387 out_data_addr = (uint32_t)target_buffer->out_buffer & 0xffffff;
1388 /*
1389 * DMA write target address register
1390 * for high order byte
1391 */
1392 IT8XXX2_I2C_RAMH2A(base) = in_data_addr >> 16;
1393 IT8XXX2_I2C_RAMHA(base) = in_data_addr >> 8;
1394 IT8XXX2_I2C_RAMLA(base) = in_data_addr;
1395 /*
1396 * DMA read target address register
1397 * for high order byte
1398 */
1399 IT8XXX2_I2C_CMD_ADDH2(base) = out_data_addr >> 16;
1400 IT8XXX2_I2C_RAMHA2(base) = out_data_addr >> 8;
1401 IT8XXX2_I2C_RAMLA2(base) = out_data_addr;
1402
1403 /* Byte counter setting */
1404 /* This register indicates byte count[10:3]. */
1405 IT8XXX2_I2C_BYTE_CNT_H(base) =
1406 CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE >> 3;
1407 /* This register indicates byte count[2:0]. */
1408 IT8XXX2_I2C_BYTE_CNT_L(base) =
1409 CONFIG_I2C_TARGET_IT8XXX2_MAX_BUF_SIZE & GENMASK(2, 0);
1410
1411 /*
1412 * The EC processor(CPU) cannot be in the k_cpu_idle() and power
1413 * policy during the transactions with the CQ mode(DMA mode).
1414 * Otherwise, the EC processor would be clock gated.
1415 */
1416 chip_block_idle();
1417 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1418
1419 /* I2C module enable and command queue mode */
1420 IT8XXX2_I2C_CTR1(base) = IT8XXX2_I2C_COMQ_EN | IT8XXX2_I2C_MDL_EN;
1421 }
1422
1423 ite_intc_isr_clear(config->i2c_irq_base);
1424 irq_enable(config->i2c_irq_base);
1425
1426 return 0;
1427 }
1428
i2c_enhance_target_unregister(const struct device * dev,struct i2c_target_config * cfg)1429 static int i2c_enhance_target_unregister(const struct device *dev,
1430 struct i2c_target_config *cfg)
1431 {
1432 const struct i2c_enhance_config *config = dev->config;
1433 struct i2c_enhance_data *data = dev->data;
1434
1435 if (!data->target_attached) {
1436 return -EINVAL;
1437 }
1438
1439 irq_disable(config->i2c_irq_base);
1440
1441 /* Permit to enter power policy and idle mode. */
1442 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1443 if (!config->target_pio_mode) {
1444 chip_permit_idle();
1445 }
1446
1447 data->target_cfg = NULL;
1448 data->target_attached = false;
1449 data->target_nack = 0;
1450
1451 return 0;
1452 }
1453 #endif
1454
1455 static const struct i2c_driver_api i2c_enhance_driver_api = {
1456 .configure = i2c_enhance_configure,
1457 .get_config = i2c_enhance_get_config,
1458 .transfer = i2c_enhance_transfer,
1459 .recover_bus = i2c_enhance_recover_bus,
1460 #ifdef CONFIG_I2C_TARGET
1461 .target_register = i2c_enhance_target_register,
1462 .target_unregister = i2c_enhance_target_unregister,
1463 #endif
1464 };
1465
1466 #ifdef CONFIG_I2C_TARGET
1467 BUILD_ASSERT(IS_ENABLED(CONFIG_I2C_TARGET_BUFFER_MODE),
1468 "When I2C target config is enabled, the buffer mode must be used.");
1469 #endif
1470
1471 #define I2C_ITE_ENHANCE_INIT(inst) \
1472 PINCTRL_DT_INST_DEFINE(inst); \
1473 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1474 50000) || \
1475 (DT_INST_PROP(inst, clock_frequency) == \
1476 I2C_BITRATE_STANDARD) || \
1477 (DT_INST_PROP(inst, clock_frequency) == \
1478 I2C_BITRATE_FAST) || \
1479 (DT_INST_PROP(inst, clock_frequency) == \
1480 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
1481 static void i2c_enhance_config_func_##inst(void); \
1482 \
1483 static const struct i2c_enhance_config i2c_enhance_cfg_##inst = { \
1484 .base = (uint8_t *)(DT_INST_REG_ADDR(inst)), \
1485 .irq_config_func = i2c_enhance_config_func_##inst, \
1486 .bitrate = DT_INST_PROP(inst, clock_frequency), \
1487 .i2c_irq_base = DT_INST_IRQN(inst), \
1488 .port = DT_INST_PROP(inst, port_num), \
1489 .channel_switch_sel = DT_INST_PROP(inst, channel_switch_sel), \
1490 .scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
1491 .sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
1492 .prescale_scl_low = DT_INST_PROP_OR(inst, prescale_scl_low, 0), \
1493 .data_hold_time = DT_INST_PROP_OR(inst, data_hold_time, 0), \
1494 .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
1495 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1496 .target_enable = DT_INST_PROP(inst, target_enable), \
1497 .target_pio_mode = DT_INST_PROP(inst, target_pio_mode), \
1498 .push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \
1499 }; \
1500 \
1501 static struct i2c_enhance_data i2c_enhance_data_##inst; \
1502 \
1503 I2C_DEVICE_DT_INST_DEFINE(inst, i2c_enhance_init, \
1504 NULL, \
1505 &i2c_enhance_data_##inst, \
1506 &i2c_enhance_cfg_##inst, \
1507 POST_KERNEL, \
1508 CONFIG_I2C_INIT_PRIORITY, \
1509 &i2c_enhance_driver_api); \
1510 \
1511 static void i2c_enhance_config_func_##inst(void) \
1512 { \
1513 IRQ_CONNECT(DT_INST_IRQN(inst), \
1514 0, \
1515 i2c_enhance_isr, \
1516 DEVICE_DT_INST_GET(inst), 0); \
1517 }
1518
1519 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_ENHANCE_INIT)
1520
