1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_ESPI_VW_H 8 #define _MEC172X_ESPI_VW_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */ 14 /* 32-bit word 0 (bits[31:0]) */ 15 #define ESPI_M2SW0_OFS 0u 16 #define ESPI_M2SW0_IDX_POS 0 17 #define ESPI_M2SW0_IDX_MASK 0xffu 18 #define ESPI_M2SW0_MTOS_SRC_POS 8u 19 #define ESPI_M2SW0_MTOS_SRC_MASK0 0x03u 20 #define ESPI_M2SW0_MTOS_SRC_MASK 0x300u 21 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u 22 #define ESPI_M2SW0_MTOS_SRC_SYS_RST 0x100u 23 #define ESPI_M2SW0_MTOS_SRC_SIO_RST 0x200u 24 #define ESPI_M2SW0_MTOS_SRC_PLTRST 0x300u 25 #define ESPI_M2SW0_MTOS_STATE_POS 12u 26 #define ESPI_M2SW0_MTOS_STATE_MASK0 0x0fu 27 #define ESPI_M2SW0_MTOS_STATE_MASK 0xf000u 28 /* 32-bit word 1 (bits[63:32]) */ 29 #define ESPI_M2SW1_OFS 4u 30 #define ESPI_M2SW1_SRC0_SEL_POS 0 31 #define ESPI_M2SW1_SRC_SEL_MASK0 0x0fu 32 #define ESPI_M2SW1_SRC0_SEL_MASK 0x0fu 33 #define ESPI_M2SW1_SRC1_SEL_POS 8 34 #define ESPI_M2SW1_SRC1_SEL_MASK 0x0f00u 35 #define ESPI_M2SW1_SRC2_SEL_POS 16 36 #define ESPI_M2SW1_SRC2_SEL_MASK 0x0f0000u 37 #define ESPI_M2SW1_SRC3_SEL_POS 24 38 #define ESPI_M2SW1_SRC3_SEL_MASK 0x0f000000u 39 /* 0 <= n < 4 */ 40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u) 41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u)) 42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u)) 43 /* 32-bit word 2 (bits[95:64]) */ 44 #define ESPI_M2SW2_OFS 8u 45 #define ESPI_M2SW2_SRC_MASK0 0x0fu 46 #define ESPI_M2SW2_SRC0_POS 0 47 #define ESPI_M2SW2_SRC0_MASK 0x0fu 48 #define ESPI_M2SW2_SRC1_POS 8u 49 #define ESPI_M2SW2_SRC1_MASK 0x0f00u 50 #define ESPI_M2SW2_SRC2_POS 16u 51 #define ESPI_M2SW2_SRC2_MASK 0x0f0000u 52 #define ESPI_M2SW2_SRC3_POS 24u 53 #define ESPI_M2SW2_SRC3_MASK 0x0f000000u 54 /* 0 <= n < 4 */ 55 #define ESPI_M2SW2_SRC_POS(n) ((n) * 8u) 56 #define ESPI_M2SW2_SRC_MASK(n) SHLU32(0xfu, ((n) * 8u)) 57 #define ESPI_M2SW2_SRC_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u)) 58 59 /* 60 * Zero based values used for above SRC_SEL fields. 61 * These values select the interrupt sensitivity for the VWire. 62 * Example: Set SRC1 to Level High 63 * 64 * r = read MSVW1 register 65 * r &= ESPI_M2SW1_SRC_SEL_MASK(1) 66 * r |= ESPI_MSVW1_SRC_SEL_VAL(1, ESPI_IRQ_SEL_LVL_HI) 67 * write r to MSVW1 register 68 */ 69 #define ESPI_IRQ_SEL_LVL_LO 0 70 #define ESPI_IRQ_SEL_LVL_HI 1 71 #define ESPI_IRQ_SEL_DIS 4 72 /* NOTE: Edge trigger modes allow VWires to wake from deep sleep */ 73 #define ESPI_IRQ_SEL_REDGE 0x0du 74 #define ESPI_IRQ_SEL_FEDGE 0x0eu 75 #define ESPI_IRQ_SEL_BEDGE 0x0fu 76 77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */ 78 /* 32-bit word 0 (bits[31:0]) */ 79 #define ESPI_S2MW0_OFS 0 80 #define ESPI_S2MW0_IDX_POS 0 81 #define ESPI_S2MW0_IDX_MASK 0xffu 82 #define ESPI_S2MW0_STOM_POS 8u 83 #define ESPI_S2MW0_STOM_SRC_POS 8u 84 #define ESPI_S2MW0_STOM_MASK0 0xf3u 85 #define ESPI_S2MW0_STOM_MASK 0xf300u 86 #define ESPI_S2MW0_STOM_SRC_MASK0 0x03u 87 #define ESPI_S2MW0_STOM_SRC_MASK 0x0300u 88 #define ESPI_S2MW0_STOM_SRC_ESPI_RST 0u 89 #define ESPI_S2MW0_STOM_SRC_SYS_RST 0x0100u 90 #define ESPI_S2MW0_STOM_SRC_SIO_RST 0x0200u 91 #define ESPI_S2MW0_STOM_SRC_PLTRST 0x0300u 92 #define ESPI_S2MW0_STOM_STATE_POS 12u 93 #define ESPI_S2MW0_STOM_STATE_MASK0 0x0fu 94 #define ESPI_S2MW0_STOM_STATE_MASK 0x0f000u 95 #define ESPI_S2MW0_CHG0_POS 16u 96 #define ESPI_S2MW0_CHG0 BIT(ESPI_S2MW0_CHG0_POS) 97 #define ESPI_S2MW0_CHG1_POS 17u 98 #define ESPI_S2MW0_CHG1 BIT(ESPI_S2MW0_CHG1_POS) 99 #define ESPI_S2MW0_CHG2_POS 18u 100 #define ESPI_S2MW0_CHG2 BIT(ESPI_S2MW0_CHG2_POS) 101 #define ESPI_S2MW0_CHG3_POS 19u 102 #define ESPI_S2MW0_CHG3 BIT(ESPI_S2MW0_CHG3_POS) 103 #define ESPI_S2MW0_CHG_ALL_POS 16u 104 #define ESPI_S2MW0_CHG_ALL_MASK0 0x0fu 105 #define ESPI_S2MW0_CHG_ALL_MASK 0x0f0000u 106 /* 0 <= n < 4 */ 107 #define ESPI_S2MW1_CHG_POS(n) ((n) + 16u) 108 #define ESPI_S2MW1_CHG(v, n) \ 109 (((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01) 110 111 /* 32-bit word 1 (bits[63:32]) */ 112 #define ESPI_S2MW1_OFS 4u 113 #define ESPI_S2MW1_SRC0_POS 0u 114 #define ESPI_S2MW1_SRC0 BIT(ESPI_S2MW1_SRC0_POS) 115 #define ESPI_S2MW1_SRC1_POS 8u 116 #define ESPI_S2MW1_SRC1 BIT(ESPI_S2MW1_SRC1_POS) 117 #define ESPI_S2MW1_SRC2_POS 16u 118 #define ESPI_S2MW1_SRC2 BIT(ESPI_S2MW1_SRC2_POS) 119 #define ESPI_S2MW1_SRC3_POS 24u 120 #define ESPI_S2MW1_SRC3 BIT(ESPI_S2MW1_SRC3_POS) 121 /* 0 <= n < 4 */ 122 #define ESPI_S2MW1_SRC_POS(n) SHLU32((n), 3) 123 #define ESPI_S2MW1_SRC(v, n) \ 124 SHLU32(((uint32_t)(v) & 0x01), (ESPI_S2MW1_SRC_POS(n))) 125 126 /** 127 * @brief eSPI Virtual Wires (ESPI_VW) 128 */ 129 130 #define ESPI_MSVW_IDX_MAX 10u 131 #define ESPI_SMVW_IDX_MAX 10u 132 133 #define ESPI_NUM_MSVW 11u 134 #define ESPI_NUM_SMVW 11u 135 136 /* 137 * ESPI MSVW interrupts 138 * GIRQ24 contains MSVW 0 - 6 139 * GIRQ25 contains MSVW 7 - 10 140 */ 141 #define MEC_ESPI_MSVW_NUM_GIRQS 2u 142 143 /* Master-to-Slave VW byte indices(offsets) */ 144 #define MSVW_INDEX_OFS 0u 145 #define MSVW_MTOS_OFS 1u 146 #define MSVW_SRC0_ISEL_OFS 4u 147 #define MSVW_SRC1_ISEL_OFS 5u 148 #define MSVW_SRC2_ISEL_OFS 6u 149 #define MSVW_SRC3_ISEL_OFS 7u 150 #define MSVW_SRC0_OFS 8u 151 #define MSVW_SRC1_OFS 9u 152 #define MSVW_SRC2_OFS 10u 153 #define MSVW_SRC3_OFS 11u 154 155 /* Slave-to-Master VW byte indices(offsets) */ 156 #define SMVW_INDEX_OFS 0u 157 #define SMVW_STOM_OFS 1u 158 #define SMVW_CHANGED_OFS 2u 159 #define SMVW_SRC0_OFS 4u 160 #define SMVW_SRC1_OFS 5u 161 #define SMVW_SRC2_OFS 6u 162 #define SMVW_SRC3_OFS 7u 163 164 165 /* Master-to-Slave Virtual Wire 96-bit register */ 166 #define MEC_MSVW_SRC0_IRQ_SEL_POS 0u 167 #define MEC_MSVW_SRC1_IRQ_SEL_POS 8u 168 #define MEC_MSVW_SRC2_IRQ_SEL_POS 16u 169 #define MEC_MSVW_SRC3_IRQ_SEL_POS 24u 170 171 #define MEC_MSVW_SRC_IRQ_SEL_MASK0 0x0fu 172 #define MEC_MSVW_SRC0_IRQ_SEL_MASK \ 173 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC0_IRQ_SEL_POS) 174 #define MEC_MSVW_SRC1_IRQ_SEL_MASK \ 175 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC1_IRQ_SEL_POS) 176 #define MEC_MSVW_SRC2_IRQ_SEL_MASK \ 177 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC2_IRQ_SEL_POS) 178 #define MEC_MSVW_SRC3_IRQ_SEL_MASK \ 179 SHLU32(MEC_MSVW_SRC_IRQ_SEL_MASK0, MEC_MSVW_SRC3_IRQ_SEL_POS) 180 181 #define MEC_MSVW_SRC_IRQ_SEL_LVL_LO 0x00u 182 #define MEC_MSVW_SRC_IRQ_SEL_LVL_HI 0x01u 183 #define MEC_MSVW_SRC_IRQ_SEL_DIS 0x04u 184 #define MEC_MSVW_SRC_IRQ_SEL_EDGE_FALL 0x0du 185 #define MEC_MSVW_SRC_IRQ_SEL_EDGE_RISE 0x0eu 186 #define MEC_MSVW_SRC_IRQ_SEL_EDGE_BOTH 0x0fu 187 188 /* 189 * 0 <= src <= 3 190 * isel = MEC_MSVW_SRC_IRQ_SEL_LVL_LO, ... 191 */ 192 #define MEC_MSVW_SRC_IRQ_SEL_VAL(src, isel) \ 193 ((uint32_t)(isel) << ((src) * 8u)) 194 195 #define MEC_MSVW_SRC0_POS 0u 196 #define MEC_MSVW_SRC1_POS 8u 197 #define MEC_MSVW_SRC2_POS 16u 198 #define MEC_MSVW_SRC3_POS 24u 199 200 #define MEC_MSVW_SRC_MASK0 0x01u 201 202 #define MEC_MSVW_SRC0_MASK BIT(0) 203 #define MEC_MSVW_SRC1_MASK BIT(8) 204 #define MEC_MSVW_SRC2_MASK BIT(16) 205 #define MEC_MSVW_SRC3_MASK BIT(24) 206 207 /* 208 * 0 <= src <= 3 209 * val = 0 or 1 210 */ 211 #define MEC_MSVW_SRC_VAL(src, val) \ 212 ((uint32_t)(val & 0x01u) << ((src) * 8u)) 213 214 /* Slave-to-Master Virtual Wire 64-bit register */ 215 216 /* MSVW helper inline functions */ 217 218 /* Interfaces to any C modules */ 219 #ifdef __cplusplus 220 extern "C" { 221 #endif 222 223 enum espi_msvw_src { 224 MSVW_SRC0 = 0u, 225 MSVW_SRC1, 226 MSVW_SRC2, 227 MSVW_SRC3 228 }; 229 230 enum espi_smvw_src { 231 SMVW_SRC0 = 0u, 232 SMVW_SRC1, 233 SMVW_SRC2, 234 SMVW_SRC3 235 }; 236 237 enum espi_msvw_irq_sel { 238 MSVW_IRQ_SEL_LVL_LO = 0x00u, 239 MSVW_IRQ_SEL_LVL_HI = 0x01u, 240 MSVW_IRQ_SEL_DIS = 0x04u, 241 MSVW_IRQ_SEL_EDGE_FALL = 0x0du, 242 MSVW_IRQ_SEL_EDGE_RISE = 0x0eu, 243 MSVW_IRQ_SEL_EDGE_BOTH = 0x0fu 244 }; 245 246 /* Used for both MSVW MTOS and SMVW STOM fields */ 247 enum espi_vw_rst_src { 248 VW_RST_SRC_ESPI_RESET = 0u, 249 VW_RST_SRC_SYS_RESET, 250 VW_RST_SRC_SIO_RESET, 251 VW_RST_SRC_PLTRST, 252 }; 253 254 enum espi_msvw_byte_idx { 255 MSVW_BI_INDEX = 0, 256 MSVW_BI_MTOS, 257 MSVW_BI_RSVD2, 258 MSVW_BI_RSVD3, 259 MSVW_BI_IRQ_SEL0, 260 MSVW_BI_IRQ_SEL1, 261 MSVW_BI_IRQ_SEL2, 262 MSVW_BI_IRQ_SEL3, 263 MSVW_BI_SRC0, 264 MSVW_BI_SRC1, 265 MSVW_BI_SRC2, 266 MSVW_BI_SRC3, 267 MSVW_IDX_MAX 268 }; 269 270 enum espi_smvw_byte_idx { 271 SMVW_BI_INDEX = 0, 272 SMVW_BI_STOM, 273 SMVW_BI_SRC_CHG, 274 SMVW_BI_RSVD3, 275 SMVW_BI_SRC0, 276 SMVW_BI_SRC1, 277 SMVW_BI_SRC2, 278 SMVW_BI_SRC3, 279 SMVW_IDX_MAX 280 }; 281 282 /** @brief eSPI 96-bit Host-to-Target Virtual Wire register */ 283 struct espi_msvw_reg { 284 volatile uint8_t INDEX; 285 volatile uint8_t MTOS; 286 uint8_t RSVD1[2]; 287 volatile uint32_t SRC_IRQ_SEL; 288 volatile uint32_t SRC; 289 }; 290 291 /** @brief eSPI 96-bit Host-to-Target Virtual Wire register as bytes */ 292 struct espi_msvwb_reg { 293 volatile uint8_t HTVWB[12]; 294 }; 295 296 /** @brief HW implements 11 Host-to-Target VW registers as an array */ 297 struct espi_msvw_ar_regs { 298 struct espi_msvw_reg MSVW[11]; 299 }; 300 301 /** @brief HW implements 11 Host-to-Target VW registers as named registers */ 302 struct espi_msvw_named_regs { 303 struct espi_msvw_reg MSVW00; 304 struct espi_msvw_reg MSVW01; 305 struct espi_msvw_reg MSVW02; 306 struct espi_msvw_reg MSVW03; 307 struct espi_msvw_reg MSVW04; 308 struct espi_msvw_reg MSVW05; 309 struct espi_msvw_reg MSVW06; 310 struct espi_msvw_reg MSVW07; 311 struct espi_msvw_reg MSVW08; 312 struct espi_msvw_reg MSVW09; 313 struct espi_msvw_reg MSVW10; 314 }; 315 316 /** @brief eSPI M2S VW registers as an array of words at 0x400F9C00 */ 317 struct espi_msvw32_regs { 318 volatile uint32_t MSVW32[11 * 3]; 319 }; 320 321 /** @brief eSPI 64-bit Target-to-Host Virtual Wire register */ 322 struct espi_smvw_reg { 323 volatile uint8_t INDEX; 324 volatile uint8_t STOM; 325 volatile uint8_t SRC_CHG; 326 uint8_t RSVD1[1]; 327 volatile uint32_t SRC; 328 }; 329 330 /** @brief eSPI 64-bit Target-to-Host Virtual Wire register as bytes */ 331 struct espi_smvwb_reg { 332 volatile uint8_t THVWB[8]; 333 }; 334 335 336 /** @brief HW implements 11 Target-to-Host VW registers as an array */ 337 struct espi_smvw_ar_regs { 338 struct espi_smvw_reg SMVW[11]; 339 }; 340 341 /** @brief HW implements 11 Target-to-Host VW registers as named registers */ 342 struct espi_smvw_named_regs { 343 struct espi_smvw_reg SMVW00; 344 struct espi_smvw_reg SMVW01; 345 struct espi_smvw_reg SMVW02; 346 struct espi_smvw_reg SMVW03; 347 struct espi_smvw_reg SMVW04; 348 struct espi_smvw_reg SMVW05; 349 struct espi_smvw_reg SMVW06; 350 struct espi_smvw_reg SMVW07; 351 struct espi_smvw_reg SMVW08; 352 struct espi_smvw_reg SMVW09; 353 struct espi_smvw_reg SMVW10; 354 }; 355 356 /** @brief eSPI S2M VW registers as an array of words at 0x400F9E00 */ 357 struct espi_smvw32_regs { 358 volatile uint32_t SMVW[11 * 2]; 359 }; 360 361 #ifdef __cplusplus 362 } 363 #endif 364 365 #endif /* #ifndef _MEC172X_ESPI_VW_H */ 366
