1 /* 2 * Copyright (c) 2020 PHYTEC Messtechnik GmbH 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * This file is based on dw1000_regs.h and dw1000_mac.c from 7 * https://github.com/Decawave/mynewt-dw1000-core.git 8 * (d6b1414f1b4527abda7521a304baa1c648244108) 9 * The content was modified and restructured to meet the 10 * coding style and resolve namespace issues. 11 * 12 * This file is derived from material that is: 13 * 14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved 15 * 16 * Licensed to the Apache Software Foundation (ASF) under one 17 * or more contributor license agreements. See the NOTICE file 18 * distributed with this work for additional information 19 * regarding copyright ownership. The ASF licenses this file 20 * to you under the Apache License, Version 2.0 (the 21 * "License"); you may not use this file except in compliance 22 * with the License. You may obtain a copy of the License at 23 * 24 * http://www.apache.org/licenses/LICENSE-2.0 25 * 26 * Unless required by applicable law or agreed to in writing, 27 * software distributed under the License is distributed on an 28 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 29 * KIND, either express or implied. See the License for the 30 * specific language governing permissions and limitations 31 * under the License. 32 */ 33 34 #ifndef ZEPHYR_INCLUDE_DW1000_REGS_H_ 35 #define ZEPHYR_INCLUDE_DW1000_REGS_H_ 36 37 /* Device ID register, includes revision info (0xDECA0130) */ 38 #define DWT_DEV_ID_ID 0x00 39 #define DWT_DEV_ID_LEN 4 40 /* Revision */ 41 #define DWT_DEV_ID_REV_MASK 0x0000000FUL 42 /* Version */ 43 #define DWT_DEV_ID_VER_MASK 0x000000F0UL 44 /* The MODEL identifies the device. The DW1000 is device type 0x01 */ 45 #define DWT_DEV_ID_MODEL_MASK 0x0000FF00UL 46 /* Register Identification Tag 0XDECA */ 47 #define DWT_DEV_ID_RIDTAG_MASK 0xFFFF0000UL 48 49 /* IEEE Extended Unique Identifier (63:0) */ 50 #define DWT_EUI_64_ID 0x01 51 #define DWT_EUI_64_OFFSET 0x00 52 #define DWT_EUI_64_LEN 8 53 54 /* PAN ID (31:16) and Short Address (15:0) */ 55 #define DWT_PANADR_ID 0x03 56 #define DWT_PANADR_LEN 4 57 #define DWT_PANADR_SHORT_ADDR_OFFSET 0 58 /* Short Address */ 59 #define DWT_PANADR_SHORT_ADDR_MASK 0x0000FFFFUL 60 #define DWT_PANADR_PAN_ID_OFFSET 2 61 /* PAN Identifier */ 62 #define DWT_PANADR_PAN_ID_MASK 0xFFFF00F0UL 63 64 #define DWT_REG_05_ID_RESERVED 0x05 65 66 /* System Configuration (31:0) */ 67 #define DWT_SYS_CFG_ID 0x04 68 #define DWT_SYS_CFG_LEN 4 69 /* Access mask to SYS_CFG_ID */ 70 #define DWT_SYS_CFG_MASK 0xF047FFFFUL 71 /* Frame filtering options all frames allowed */ 72 #define DWT_SYS_CFG_FF_ALL_EN 0x000001FEUL 73 /* Frame Filtering Enable. This bit enables the frame filtering functionality */ 74 #define DWT_SYS_CFG_FFE 0x00000001UL 75 /* Frame Filtering Behave as a Co-ordinator */ 76 #define DWT_SYS_CFG_FFBC 0x00000002UL 77 /* Frame Filtering Allow Beacon frame reception */ 78 #define DWT_SYS_CFG_FFAB 0x00000004UL 79 /* Frame Filtering Allow Data frame reception */ 80 #define DWT_SYS_CFG_FFAD 0x00000008UL 81 /* Frame Filtering Allow Acknowledgment frame reception */ 82 #define DWT_SYS_CFG_FFAA 0x00000010UL 83 /* Frame Filtering Allow MAC command frame reception */ 84 #define DWT_SYS_CFG_FFAM 0x00000020UL 85 /* Frame Filtering Allow Reserved frame types */ 86 #define DWT_SYS_CFG_FFAR 0x00000040UL 87 /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */ 88 #define DWT_SYS_CFG_FFA4 0x00000080UL 89 /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */ 90 #define DWT_SYS_CFG_FFA5 0x00000100UL 91 /* Host interrupt polarity */ 92 #define DWT_SYS_CFG_HIRQ_POL 0x00000200UL 93 /* SPI data launch edge */ 94 #define DWT_SYS_CFG_SPI_EDGE 0x00000400UL 95 /* Disable frame check error handling */ 96 #define DWT_SYS_CFG_DIS_FCE 0x00000800UL 97 /* Disable Double RX Buffer */ 98 #define DWT_SYS_CFG_DIS_DRXB 0x00001000UL 99 /* Disable receiver abort on PHR error */ 100 #define DWT_SYS_CFG_DIS_PHE 0x00002000UL 101 /* Disable Receiver Abort on RSD error */ 102 #define DWT_SYS_CFG_DIS_RSDE 0x00004000UL 103 /* initial seed value for the FCS generation and checking function */ 104 #define DWT_SYS_CFG_FCS_INIT2F 0x00008000UL 105 #define DWT_SYS_CFG_PHR_MODE_SHFT 16 106 /* Standard Frame mode */ 107 #define DWT_SYS_CFG_PHR_MODE_00 0x00000000UL 108 /* Long Frames mode */ 109 #define DWT_SYS_CFG_PHR_MODE_11 0x00030000UL 110 /* Disable Smart TX Power control */ 111 #define DWT_SYS_CFG_DIS_STXP 0x00040000UL 112 /* Receiver Mode 110 kbps data rate */ 113 #define DWT_SYS_CFG_RXM110K 0x00400000UL 114 /* Receive Wait Timeout Enable. */ 115 #define DWT_SYS_CFG_RXWTOE 0x10000000UL 116 /* 117 * Receiver Auto-Re-enable. 118 * This bit is used to cause the receiver to re-enable automatically 119 */ 120 #define DWT_SYS_CFG_RXAUTR 0x20000000UL 121 /* Automatic Acknowledgement Enable */ 122 #define DWT_SYS_CFG_AUTOACK 0x40000000UL 123 /* Automatic Acknowledgement Pending bit control */ 124 #define DWT_SYS_CFG_AACKPEND 0x80000000UL 125 126 /* System Time Counter (40-bit) */ 127 #define DWT_SYS_TIME_ID 0x06 128 #define DWT_SYS_TIME_OFFSET 0x00 129 /* Note 40 bit register */ 130 #define DWT_SYS_TIME_LEN 5 131 132 #define DWT_REG_07_ID_RESERVED 0x07 133 134 /* Transmit Frame Control */ 135 #define DWT_TX_FCTRL_ID 0x08 136 /* Note 40 bit register */ 137 #define DWT_TX_FCTRL_LEN 5 138 /* Bit mask to access Transmit Frame Length */ 139 #define DWT_TX_FCTRL_TFLEN_MASK 0x0000007FUL 140 /* Bit mask to access Transmit Frame Length Extension */ 141 #define DWT_TX_FCTRL_TFLE_MASK 0x00000380UL 142 /* Bit mask to access Frame Length field */ 143 #define DWT_TX_FCTRL_FLE_MASK 0x000003FFUL 144 /* Bit mask to access Transmit Bit Rate */ 145 #define DWT_TX_FCTRL_TXBR_MASK 0x00006000UL 146 /* Bit mask to access Transmit Pulse Repetition Frequency */ 147 #define DWT_TX_FCTRL_TXPRF_MASK 0x00030000UL 148 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */ 149 #define DWT_TX_FCTRL_TXPSR_MASK 0x000C0000UL 150 /* Bit mask to access Preamble Extension */ 151 #define DWT_TX_FCTRL_PE_MASK 0x00300000UL 152 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */ 153 #define DWT_TX_FCTRL_TXPSR_PE_MASK 0x003C0000UL 154 /* FSCTRL has fields which should always be writen zero */ 155 #define DWT_TX_FCTRL_SAFE_MASK_32 0xFFFFE3FFUL 156 /* Transmit Bit Rate = 110k */ 157 #define DWT_TX_FCTRL_TXBR_110k 0x00000000UL 158 /* Transmit Bit Rate = 850k */ 159 #define DWT_TX_FCTRL_TXBR_850k 0x00002000UL 160 /* Transmit Bit Rate = 6.8M */ 161 #define DWT_TX_FCTRL_TXBR_6M 0x00004000UL 162 /* Shift to access Data Rate field */ 163 #define DWT_TX_FCTRL_TXBR_SHFT 13 164 /* Transmit Ranging enable */ 165 #define DWT_TX_FCTRL_TR 0x00008000UL 166 /* Shift to access Ranging bit */ 167 #define DWT_TX_FCTRL_TR_SHFT 15 168 /* Shift to access Pulse Repetition Frequency field */ 169 #define DWT_TX_FCTRL_TXPRF_SHFT 16 170 /* Transmit Pulse Repetition Frequency = 4 Mhz */ 171 #define DWT_TX_FCTRL_TXPRF_4M 0x00000000UL 172 /* Transmit Pulse Repetition Frequency = 16 Mhz */ 173 #define DWT_TX_FCTRL_TXPRF_16M 0x00010000UL 174 /* Transmit Pulse Repetition Frequency = 64 Mhz */ 175 #define DWT_TX_FCTRL_TXPRF_64M 0x00020000UL 176 /* Shift to access Preamble Symbol Repetitions field */ 177 #define DWT_TX_FCTRL_TXPSR_SHFT 18 178 /* 179 * shift to access Preamble length Extension to allow specification 180 * of non-standard values 181 */ 182 #define DWT_TX_FCTRL_PE_SHFT 20 183 /* Bit mask to access Preamble Extension = 16 */ 184 #define DWT_TX_FCTRL_TXPSR_PE_16 0x00000000UL 185 /* Bit mask to access Preamble Extension = 64 */ 186 #define DWT_TX_FCTRL_TXPSR_PE_64 0x00040000UL 187 /* Bit mask to access Preamble Extension = 128 */ 188 #define DWT_TX_FCTRL_TXPSR_PE_128 0x00140000UL 189 /* Bit mask to access Preamble Extension = 256 */ 190 #define DWT_TX_FCTRL_TXPSR_PE_256 0x00240000UL 191 /* Bit mask to access Preamble Extension = 512 */ 192 #define DWT_TX_FCTRL_TXPSR_PE_512 0x00340000UL 193 /* Bit mask to access Preamble Extension = 1024 */ 194 #define DWT_TX_FCTRL_TXPSR_PE_1024 0x00080000UL 195 /* Bit mask to access Preamble Extension = 1536 */ 196 #define DWT_TX_FCTRL_TXPSR_PE_1536 0x00180000UL 197 /* Bit mask to access Preamble Extension = 2048 */ 198 #define DWT_TX_FCTRL_TXPSR_PE_2048 0x00280000UL 199 /* Bit mask to access Preamble Extension = 4096 */ 200 #define DWT_TX_FCTRL_TXPSR_PE_4096 0x000C0000UL 201 /* Shift to access transmit buffer index offset */ 202 #define DWT_TX_FCTRL_TXBOFFS_SHFT 22 203 /* Bit mask to access Transmit buffer index offset 10-bit field */ 204 #define DWT_TX_FCTRL_TXBOFFS_MASK 0xFFC00000UL 205 /* Bit mask to access Inter-Frame Spacing field */ 206 #define DWT_TX_FCTRL_IFSDELAY_MASK 0xFF00000000ULL 207 208 /* Transmit Data Buffer */ 209 #define DWT_TX_BUFFER_ID 0x09 210 #define DWT_TX_BUFFER_LEN 1024 211 212 /* Delayed Send or Receive Time (40-bit) */ 213 #define DWT_DX_TIME_ID 0x0A 214 #define DWT_DX_TIME_LEN 5 215 216 #define DWT_REG_0B_ID_RESERVED 0x0B 217 218 /* Receive Frame Wait Timeout Period */ 219 #define DWT_RX_FWTO_ID 0x0C 220 #define DWT_RX_FWTO_OFFSET 0x00 221 #define DWT_RX_FWTO_LEN 2 222 #define DWT_RX_FWTO_MASK 0xFFFF 223 224 /* System Control Register */ 225 #define DWT_SYS_CTRL_ID 0x0D 226 #define DWT_SYS_CTRL_OFFSET 0x00 227 #define DWT_SYS_CTRL_LEN 4 228 /* 229 * System Control Register access mask 230 * (all unused fields should always be writen as zero) 231 */ 232 #define DWT_SYS_CTRL_MASK_32 0x010003CFUL 233 /* Suppress Auto-FCS Transmission (on this frame) */ 234 #define DWT_SYS_CTRL_SFCST 0x00000001UL 235 /* Start Transmitting Now */ 236 #define DWT_SYS_CTRL_TXSTRT 0x00000002UL 237 /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */ 238 #define DWT_SYS_CTRL_TXDLYS 0x00000004UL 239 /* Cancel Suppression of auto-FCS transmission (on the current frame) */ 240 #define DWT_SYS_CTRL_CANSFCS 0x00000008UL 241 /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */ 242 #define DWT_SYS_CTRL_TRXOFF 0x00000040UL 243 /* Wait for Response */ 244 #define DWT_SYS_CTRL_WAIT4RESP 0x00000080UL 245 /* Enable Receiver Now */ 246 #define DWT_SYS_CTRL_RXENAB 0x00000100UL 247 /* 248 * Receiver Delayed Enable 249 * (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment 250 */ 251 #define DWT_SYS_CTRL_RXDLYE 0x00000200UL 252 /* 253 * Host side receiver buffer pointer toggle - toggles 0/1 254 * host side data set pointer 255 */ 256 #define DWT_SYS_CTRL_HSRBTOGGLE 0x01000000UL 257 #define DWT_SYS_CTRL_HRBT DWT_SYS_CTRL_HSRBTOGGLE 258 #define DWT_SYS_CTRL_HRBT_OFFSET 3 259 260 /* System Event Mask Register */ 261 #define DWT_SYS_MASK_ID 0x0E 262 #define DWT_SYS_MASK_LEN 4 263 /* 264 * System Event Mask Register access mask 265 * (all unused fields should always be writen as zero) 266 */ 267 #define DWT_SYS_MASK_MASK_32 0x3FF7FFFEUL 268 /* Mask clock PLL lock event */ 269 #define DWT_SYS_MASK_MCPLOCK 0x00000002UL 270 /* Mask clock PLL lock event */ 271 #define DWT_SYS_MASK_MESYNCR 0x00000004UL 272 /* Mask automatic acknowledge trigger event */ 273 #define DWT_SYS_MASK_MAAT 0x00000008UL 274 /* Mask transmit frame begins event */ 275 #define DWT_SYS_MASK_MTXFRB 0x00000010UL 276 /* Mask transmit preamble sent event */ 277 #define DWT_SYS_MASK_MTXPRS 0x00000020UL 278 /* Mask transmit PHY Header Sent event */ 279 #define DWT_SYS_MASK_MTXPHS 0x00000040UL 280 /* Mask transmit frame sent event */ 281 #define DWT_SYS_MASK_MTXFRS 0x00000080UL 282 /* Mask receiver preamble detected event */ 283 #define DWT_SYS_MASK_MRXPRD 0x00000100UL 284 /* Mask receiver SFD detected event */ 285 #define DWT_SYS_MASK_MRXSFDD 0x00000200UL 286 /* Mask LDE processing done event */ 287 #define DWT_SYS_MASK_MLDEDONE 0x00000400UL 288 /* Mask receiver PHY header detect event */ 289 #define DWT_SYS_MASK_MRXPHD 0x00000800UL 290 /* Mask receiver PHY header error event */ 291 #define DWT_SYS_MASK_MRXPHE 0x00001000UL 292 /* Mask receiver data frame ready event */ 293 #define DWT_SYS_MASK_MRXDFR 0x00002000UL 294 /* Mask receiver FCS good event */ 295 #define DWT_SYS_MASK_MRXFCG 0x00004000UL 296 /* Mask receiver FCS error event */ 297 #define DWT_SYS_MASK_MRXFCE 0x00008000UL 298 /* Mask receiver Reed Solomon Frame Sync Loss event */ 299 #define DWT_SYS_MASK_MRXRFSL 0x00010000UL 300 /* Mask Receive Frame Wait Timeout event */ 301 #define DWT_SYS_MASK_MRXRFTO 0x00020000UL 302 /* Mask leading edge detection processing error event */ 303 #define DWT_SYS_MASK_MLDEERR 0x00040000UL 304 /* Mask Receiver Overrun event */ 305 #define DWT_SYS_MASK_MRXOVRR 0x00100000UL 306 /* Mask Preamble detection timeout event */ 307 #define DWT_SYS_MASK_MRXPTO 0x00200000UL 308 /* Mask GPIO interrupt event */ 309 #define DWT_SYS_MASK_MGPIOIRQ 0x00400000UL 310 /* Mask SLEEP to INIT event */ 311 #define DWT_SYS_MASK_MSLP2INIT 0x00800000UL 312 /* Mask RF PLL Loosing Lock warning event */ 313 #define DWT_SYS_MASK_MRFPLLLL 0x01000000UL 314 /* Mask Clock PLL Loosing Lock warning event */ 315 #define DWT_SYS_MASK_MCPLLLL 0x02000000UL 316 /* Mask Receive SFD timeout event */ 317 #define DWT_SYS_MASK_MRXSFDTO 0x04000000UL 318 /* Mask Half Period Delay Warning event */ 319 #define DWT_SYS_MASK_MHPDWARN 0x08000000UL 320 /* Mask Transmit Buffer Error event */ 321 #define DWT_SYS_MASK_MTXBERR 0x10000000UL 322 /* Mask Automatic Frame Filtering rejection event */ 323 #define DWT_SYS_MASK_MAFFREJ 0x20000000UL 324 325 /* System event Status Register */ 326 #define DWT_SYS_STATUS_ID 0x0F 327 #define DWT_SYS_STATUS_OFFSET 0x00 328 /* Note 40 bit register */ 329 #define DWT_SYS_STATUS_LEN 5 330 /* 331 * System event Status Register access mask 332 * (all unused fields should always be writen as zero) 333 */ 334 #define DWT_SYS_STATUS_MASK_32 0xFFF7FFFFUL 335 /* Interrupt Request Status READ ONLY */ 336 #define DWT_SYS_STATUS_IRQS 0x00000001UL 337 /* Clock PLL Lock */ 338 #define DWT_SYS_STATUS_CPLOCK 0x00000002UL 339 /* External Sync Clock Reset */ 340 #define DWT_SYS_STATUS_ESYNCR 0x00000004UL 341 /* Automatic Acknowledge Trigger */ 342 #define DWT_SYS_STATUS_AAT 0x00000008UL 343 /* Transmit Frame Begins */ 344 #define DWT_SYS_STATUS_TXFRB 0x00000010UL 345 /* Transmit Preamble Sent */ 346 #define DWT_SYS_STATUS_TXPRS 0x00000020UL 347 /* Transmit PHY Header Sent */ 348 #define DWT_SYS_STATUS_TXPHS 0x00000040UL 349 /* 350 * Transmit Frame Sent: 351 * This is set when the transmitter has completed the sending of a frame 352 */ 353 #define DWT_SYS_STATUS_TXFRS 0x00000080UL 354 /* Receiver Preamble Detected status */ 355 #define DWT_SYS_STATUS_RXPRD 0x00000100UL 356 /* Receiver Start Frame Delimiter Detected. */ 357 #define DWT_SYS_STATUS_RXSFDD 0x00000200UL 358 /* LDE processing done */ 359 #define DWT_SYS_STATUS_LDEDONE 0x00000400UL 360 /* Receiver PHY Header Detect */ 361 #define DWT_SYS_STATUS_RXPHD 0x00000800UL 362 /* Receiver PHY Header Error */ 363 #define DWT_SYS_STATUS_RXPHE 0x00001000UL 364 /* Receiver Data Frame Ready */ 365 #define DWT_SYS_STATUS_RXDFR 0x00002000UL 366 /* Receiver FCS Good */ 367 #define DWT_SYS_STATUS_RXFCG 0x00004000UL 368 /* Receiver FCS Error */ 369 #define DWT_SYS_STATUS_RXFCE 0x00008000UL 370 /* Receiver Reed Solomon Frame Sync Loss */ 371 #define DWT_SYS_STATUS_RXRFSL 0x00010000UL 372 /* Receive Frame Wait Timeout */ 373 #define DWT_SYS_STATUS_RXRFTO 0x00020000UL 374 /* Leading edge detection processing error */ 375 #define DWT_SYS_STATUS_LDEERR 0x00040000UL 376 /* bit19 reserved */ 377 #define DWT_SYS_STATUS_reserved 0x00080000UL 378 /* Receiver Overrun */ 379 #define DWT_SYS_STATUS_RXOVRR 0x00100000UL 380 /* Preamble detection timeout */ 381 #define DWT_SYS_STATUS_RXPTO 0x00200000UL 382 /* GPIO interrupt */ 383 #define DWT_SYS_STATUS_GPIOIRQ 0x00400000UL 384 /* SLEEP to INIT */ 385 #define DWT_SYS_STATUS_SLP2INIT 0x00800000UL 386 /* RF PLL Losing Lock */ 387 #define DWT_SYS_STATUS_RFPLL_LL 0x01000000UL 388 /* Clock PLL Losing Lock */ 389 #define DWT_SYS_STATUS_CLKPLL_LL 0x02000000UL 390 /* Receive SFD timeout */ 391 #define DWT_SYS_STATUS_RXSFDTO 0x04000000UL 392 /* Half Period Delay Warning */ 393 #define DWT_SYS_STATUS_HPDWARN 0x08000000UL 394 /* Transmit Buffer Error */ 395 #define DWT_SYS_STATUS_TXBERR 0x10000000UL 396 /* Automatic Frame Filtering rejection */ 397 #define DWT_SYS_STATUS_AFFREJ 0x20000000UL 398 /* Host Side Receive Buffer Pointer */ 399 #define DWT_SYS_STATUS_HSRBP 0x40000000UL 400 /* IC side Receive Buffer Pointer READ ONLY */ 401 #define DWT_SYS_STATUS_ICRBP 0x80000000UL 402 /* Receiver Reed-Solomon Correction Status */ 403 #define DWT_SYS_STATUS_RXRSCS 0x0100000000ULL 404 /* Receiver Preamble Rejection */ 405 #define DWT_SYS_STATUS_RXPREJ 0x0200000000ULL 406 /* Transmit power up time error */ 407 #define DWT_SYS_STATUS_TXPUTE 0x0400000000ULL 408 /* 409 * These bits are the 16 high bits of status register TXPUTE and 410 * HPDWARN flags 411 */ 412 #define DWT_SYS_STATUS_TXERR (0x0408) 413 /* All RX events after a correct packet reception mask. */ 414 #define DWT_SYS_STATUS_ALL_RX_GOOD (DWT_SYS_STATUS_RXDFR | \ 415 DWT_SYS_STATUS_RXFCG | \ 416 DWT_SYS_STATUS_RXPRD | \ 417 DWT_SYS_STATUS_RXSFDD | \ 418 DWT_SYS_STATUS_RXPHD) 419 /* All TX events mask. */ 420 #define DWT_SYS_STATUS_ALL_TX (DWT_SYS_STATUS_AAT | \ 421 DWT_SYS_STATUS_TXFRB | \ 422 DWT_SYS_STATUS_TXPRS | \ 423 DWT_SYS_STATUS_TXPHS | \ 424 DWT_SYS_STATUS_TXFRS) 425 /* All double buffer events mask. */ 426 #define DWT_SYS_STATUS_ALL_DBLBUFF (DWT_SYS_STATUS_RXDFR | \ 427 DWT_SYS_STATUS_RXFCG) 428 /* All RX errors mask. */ 429 #define DWT_SYS_STATUS_ALL_RX_ERR (DWT_SYS_STATUS_RXPHE | \ 430 DWT_SYS_STATUS_RXFCE | \ 431 DWT_SYS_STATUS_RXRFSL | \ 432 DWT_SYS_STATUS_RXOVRR | \ 433 DWT_SYS_STATUS_RXSFDTO | \ 434 DWT_SYS_STATUS_AFFREJ) 435 #define DWT_SYS_MASK_ALL_RX_ERR (DWT_SYS_MASK_MRXPHE | \ 436 DWT_SYS_MASK_MRXFCE | \ 437 DWT_SYS_MASK_MRXRFSL | \ 438 DWT_SYS_STATUS_RXOVRR | \ 439 DWT_SYS_MASK_MRXSFDTO | \ 440 DWT_SYS_MASK_MAFFREJ) 441 /* 442 * User defined RX timeouts 443 * (frame wait timeout and preamble detect timeout) mask. 444 */ 445 #define DWT_SYS_STATUS_ALL_RX_TO (DWT_SYS_STATUS_RXRFTO | \ 446 DWT_SYS_STATUS_RXPTO) 447 #define DWT_SYS_MASK_ALL_RX_TO (DWT_SYS_MASK_MRXRFTO | \ 448 DWT_SYS_MASK_MRXPTO) 449 450 /* RX Frame Information (in double buffer set) */ 451 #define DWT_RX_FINFO_ID 0x10 452 #define DWT_RX_FINFO_OFFSET 0x00 453 #define DWT_RX_FINFO_LEN 4 454 /* 455 * System event Status Register access mask 456 * (all unused fields should always be writen as zero) 457 */ 458 #define DWT_RX_FINFO_MASK_32 0xFFFFFBFFUL 459 /* Receive Frame Length (0 to 127) */ 460 #define DWT_RX_FINFO_RXFLEN_MASK 0x0000007FUL 461 /* Receive Frame Length Extension (0 to 7)<<7 */ 462 #define DWT_RX_FINFO_RXFLE_MASK 0x00000380UL 463 /* Receive Frame Length Extension (0 to 1023) */ 464 #define DWT_RX_FINFO_RXFL_MASK_1023 0x000003FFUL 465 466 /* Receive Non-Standard Preamble Length */ 467 #define DWT_RX_FINFO_RXNSPL_MASK 0x00001800UL 468 /* 469 * RX Preamble Repetition. 470 * 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols 471 */ 472 #define DWT_RX_FINFO_RXPSR_MASK 0x000C0000UL 473 474 /* Receive Preamble Length = RXPSR+RXNSPL */ 475 #define DWT_RX_FINFO_RXPEL_MASK 0x000C1800UL 476 /* Receive Preamble length = 64 */ 477 #define DWT_RX_FINFO_RXPEL_64 0x00040000UL 478 /* Receive Preamble length = 128 */ 479 #define DWT_RX_FINFO_RXPEL_128 0x00040800UL 480 /* Receive Preamble length = 256 */ 481 #define DWT_RX_FINFO_RXPEL_256 0x00041000UL 482 /* Receive Preamble length = 512 */ 483 #define DWT_RX_FINFO_RXPEL_512 0x00041800UL 484 /* Receive Preamble length = 1024 */ 485 #define DWT_RX_FINFO_RXPEL_1024 0x00080000UL 486 /* Receive Preamble length = 1536 */ 487 #define DWT_RX_FINFO_RXPEL_1536 0x00080800UL 488 /* Receive Preamble length = 2048 */ 489 #define DWT_RX_FINFO_RXPEL_2048 0x00081000UL 490 /* Receive Preamble length = 4096 */ 491 #define DWT_RX_FINFO_RXPEL_4096 0x000C0000UL 492 493 /* Receive Bit Rate report. This field reports the received bit rate */ 494 #define DWT_RX_FINFO_RXBR_MASK 0x00006000UL 495 /* Received bit rate = 110 kbps */ 496 #define DWT_RX_FINFO_RXBR_110k 0x00000000UL 497 /* Received bit rate = 850 kbps */ 498 #define DWT_RX_FINFO_RXBR_850k 0x00002000UL 499 /* Received bit rate = 6.8 Mbps */ 500 #define DWT_RX_FINFO_RXBR_6M 0x00004000UL 501 #define DWT_RX_FINFO_RXBR_SHIFT 13 502 503 /* 504 * Receiver Ranging. Ranging bit in the received PHY header 505 * identifying the frame as a ranging packet. 506 */ 507 #define DWT_RX_FINFO_RNG 0x00008000UL 508 #define DWT_RX_FINFO_RNG_SHIFT 15 509 510 /* RX Pulse Repetition Rate report */ 511 #define DWT_RX_FINFO_RXPRF_MASK 0x00030000UL 512 /* PRF being employed in the receiver = 16M */ 513 #define DWT_RX_FINFO_RXPRF_16M 0x00010000UL 514 /* PRF being employed in the receiver = 64M */ 515 #define DWT_RX_FINFO_RXPRF_64M 0x00020000UL 516 #define DWT_RX_FINFO_RXPRF_SHIFT 16 517 518 /* Preamble Accumulation Count */ 519 #define DWT_RX_FINFO_RXPACC_MASK 0xFFF00000UL 520 #define DWT_RX_FINFO_RXPACC_SHIFT 20 521 522 /* Receive Data Buffer (in double buffer set) */ 523 #define DWT_RX_BUFFER_ID 0x11 524 #define DWT_RX_BUFFER_LEN 1024 525 526 /* Rx Frame Quality information (in double buffer set) */ 527 #define DWT_RX_FQUAL_ID 0x12 528 /* Note 64 bit register */ 529 #define DWT_RX_FQUAL_LEN 8 530 /* Standard Deviation of Noise */ 531 #define DWT_RX_EQUAL_STD_NOISE_MASK 0x0000FFFFULL 532 #define DWT_RX_EQUAL_STD_NOISE_SHIFT 0 533 #define DWT_STD_NOISE_MASK DWT_RX_EQUAL_STD_NOISE_MASK 534 #define DWT_STD_NOISE_SHIFT DWT_RX_EQUAL_STD_NOISE_SHIFT 535 /* First Path Amplitude point 2 */ 536 #define DWT_RX_EQUAL_FP_AMPL2_MASK 0xFFFF0000ULL 537 #define DWT_RX_EQUAL_FP_AMPL2_SHIFT 16 538 #define DWT_FP_AMPL2_MASK DWT_RX_EQUAL_FP_AMPL2_MASK 539 #define DWT_FP_AMPL2_SHIFT DWT_RX_EQUAL_FP_AMPL2_SHIFT 540 /* First Path Amplitude point 3 */ 541 #define DWT_RX_EQUAL_PP_AMPL3_MASK 0x0000FFFF00000000ULL 542 #define DWT_RX_EQUAL_PP_AMPL3_SHIFT 32 543 #define DWT_PP_AMPL3_MASK DWT_RX_EQUAL_PP_AMPL3_MASK 544 #define DWT_PP_AMPL3_SHIFT DWT_RX_EQUAL_PP_AMPL3_SHIFT 545 /* Channel Impulse Response Max Growth */ 546 #define DWT_RX_EQUAL_CIR_MXG_MASK 0xFFFF000000000000ULL 547 #define DWT_RX_EQUAL_CIR_MXG_SHIFT 48 548 #define DWT_CIR_MXG_MASK DWT_RX_EQUAL_CIR_MXG_MASK 549 #define DWT_CIR_MXG_SHIFT DWT_RX_EQUAL_CIR_MXG_SHIFT 550 551 /* Receiver Time Tracking Interval (in double buffer set) */ 552 #define DWT_RX_TTCKI_ID 0x13 553 #define DWT_RX_TTCKI_LEN 4 554 555 /* Receiver Time Tracking Offset (in double buffer set) */ 556 #define DWT_RX_TTCKO_ID 0x14 557 /* Note 40 bit register */ 558 #define DWT_RX_TTCKO_LEN 5 559 /* 560 * Receiver Time Tracking Offset access mask 561 * (all unused fields should always be writen as zero) 562 */ 563 #define DWT_RX_TTCKO_MASK_32 0xFF07FFFFUL 564 /* RX time tracking offset. This RXTOFS value is a 19-bit signed quantity */ 565 #define DWT_RX_TTCKO_RXTOFS_MASK 0x0007FFFFUL 566 /* This 8-bit field reports an internal re-sampler delay value */ 567 #define DWT_RX_TTCKO_RSMPDEL_MASK 0xFF000000UL 568 /* 569 * This 7-bit field reports the receive carrier phase adjustment 570 * at time the ranging timestamp is made. 571 */ 572 #define DWT_RX_TTCKO_RCPHASE_MASK 0x7F0000000000ULL 573 574 /* Receive Message Time of Arrival (in double buffer set) */ 575 #define DWT_RX_TIME_ID 0x15 576 #define DWT_RX_TIME_LLEN 14 577 /* read only 5 bytes (the adjusted timestamp (40:0)) */ 578 #define DWT_RX_TIME_RX_STAMP_LEN 5 579 #define DWT_RX_STAMP_LEN DWT_RX_TIME_RX_STAMP_LEN 580 /* byte 0..4 40 bit Reports the fully adjusted time of reception. */ 581 #define DWT_RX_TIME_RX_STAMP_OFFSET 0 582 /* byte 5..6 16 bit First path index. */ 583 #define DWT_RX_TIME_FP_INDEX_OFFSET 5 584 /* byte 7..8 16 bit First Path Amplitude point 1 */ 585 #define DWT_RX_TIME_FP_AMPL1_OFFSET 7 586 /* byte 9..13 40 bit Raw Timestamp for the frame */ 587 #define DWT_RX_TIME_FP_RAWST_OFFSET 9 588 589 #define DWT_REG_16_ID_RESERVED 0x16 590 591 /* Transmit Message Time of Sending */ 592 #define DWT_TX_TIME_ID 0x17 593 #define DWT_TX_TIME_LLEN 10 594 /* 40-bits = 5 bytes */ 595 #define DWT_TX_TIME_TX_STAMP_LEN 5 596 #define DWT_TX_STAMP_LEN DWT_TX_TIME_TX_STAMP_LEN 597 /* byte 0..4 40 bit Reports the fully adjusted time of transmission */ 598 #define DWT_TX_TIME_TX_STAMP_OFFSET 0 599 /* byte 5..9 40 bit Raw Timestamp for the frame */ 600 #define DWT_TX_TIME_TX_RAWST_OFFSET 5 601 602 /* 16-bit Delay from Transmit to Antenna */ 603 #define DWT_TX_ANTD_ID 0x18 604 #define DWT_TX_ANTD_OFFSET 0x00 605 #define DWT_TX_ANTD_LEN 2 606 607 /* System State information READ ONLY */ 608 #define DWT_SYS_STATE_ID 0x19 609 #define DWT_SYS_STATE_LEN 5 610 611 /* 7:0 TX _STATE Bits 3:0 */ 612 #define DWT_TX_STATE_OFFSET 0x00 613 #define DWT_TX_STATE_MASK 0x07 614 #define DWT_TX_STATE_IDLE 0x00 615 #define DWT_TX_STATE_PREAMBLE 0x01 616 #define DWT_TX_STATE_SFD 0x02 617 #define DWT_TX_STATE_PHR 0x03 618 #define DWT_TX_STATE_SDE 0x04 619 #define DWT_TX_STATE_DATA 0x05 620 #define DWT_TX_STATE_RSP_DATE 0x06 621 #define DWT_TX_STATE_TAIL 0x07 622 623 #define DWT_RX_STATE_OFFSET 0x01 624 #define DWT_RX_STATE_IDLE 0x00 625 #define DWT_RX_STATE_START_ANALOG 0x01 626 #define DWT_RX_STATE_RX_RDY 0x04 627 #define DWT_RX_STATE_PREAMBLE_FOUND 0x05 628 #define DWT_RX_STATE_PRMBL_TIMEOUT 0x06 629 #define DWT_RX_STATE_SFD_FOUND 0x07 630 #define DWT_RX_STATE_CNFG_PHR_RX 0x08 631 #define DWT_RX_STATE_PHR_RX_STRT 0x09 632 #define DWT_RX_STATE_DATA_RATE_RDY 0x0A 633 #define DWT_RX_STATE_DATA_RX_SEQ 0x0C 634 #define DWT_RX_STATE_CNFG_DATA_RX 0x0D 635 #define DWT_RX_STATE_PHR_NOT_OK 0x0E 636 #define DWT_RX_STATE_LAST_SYMBOL 0x0F 637 #define DWT_RX_STATE_WAIT_RSD_DONE 0x10 638 #define DWT_RX_STATE_RSD_OK 0x11 639 #define DWT_RX_STATE_RSD_NOT_OK 0x12 640 #define DWT_RX_STATE_RECONFIG_110 0x13 641 #define DWT_RX_STATE_WAIT_110_PHR 0x14 642 643 #define DWT_PMSC_STATE_OFFSET 0x02 644 #define DWT_PMSC_STATE_INIT 0x00 645 #define DWT_PMSC_STATE_IDLE 0x01 646 #define DWT_PMSC_STATE_TX_WAIT 0x02 647 #define DWT_PMSC_STATE_RX_WAIT 0x03 648 #define DWT_PMSC_STATE_TX 0x04 649 #define DWT_PMSC_STATE_RX 0x05 650 651 /* 652 * Acknowledge (31:24 preamble symbol delay before auto ACK is sent) and 653 * response (19:0 - unit 1us) timer 654 */ 655 /* Acknowledgement Time and Response Time */ 656 #define DWT_ACK_RESP_T_ID 0x1A 657 #define DWT_ACK_RESP_T_LEN 4 658 /* Acknowledgement Time and Response access mask */ 659 #define DWT_ACK_RESP_T_MASK 0xFF0FFFFFUL 660 #define DWT_ACK_RESP_T_W4R_TIM_OFFSET 0 661 /* Wait-for-Response turn-around Time 20 bit field */ 662 #define DWT_ACK_RESP_T_W4R_TIM_MASK 0x000FFFFFUL 663 #define DWT_W4R_TIM_MASK DWT_ACK_RESP_T_W4R_TIM_MASK 664 #define DWT_ACK_RESP_T_ACK_TIM_OFFSET 3 665 /* Auto-Acknowledgement turn-around Time */ 666 #define DWT_ACK_RESP_T_ACK_TIM_MASK 0xFF000000UL 667 #define DWT_ACK_TIM_MASK DWT_ACK_RESP_T_ACK_TIM_MASK 668 669 #define DWT_REG_1B_ID_RESERVED 0x1B 670 #define DWT_REG_1C_ID_RESERVED 0x1C 671 672 /* Sniff Mode Configuration */ 673 #define DWT_RX_SNIFF_ID 0x1D 674 #define DWT_RX_SNIFF_OFFSET 0x00 675 #define DWT_RX_SNIFF_LEN 4 676 #define DWT_RX_SNIFF_MASK 0x0000FF0FUL 677 /* SNIFF Mode ON time. Specified in units of PAC */ 678 #define DWT_RX_SNIFF_SNIFF_ONT_MASK 0x0000000FUL 679 #define DWT_SNIFF_ONT_MASK DWT_RX_SNIFF_SNIFF_ONT_MASK 680 /* 681 * SNIFF Mode OFF time specified in units of approximately 1mkS, 682 * or 128 system clock cycles. 683 */ 684 #define DWT_RX_SNIFF_SNIFF_OFFT_MASK 0x0000FF00UL 685 #define DWT_SNIFF_OFFT_MASK DWT_RX_SNIFF_SNIFF_OFFT_MASK 686 687 /* TX Power Control */ 688 #define DWT_TX_POWER_ID 0x1E 689 #define DWT_TX_POWER_LEN 4 690 /* 691 * Mask and shift definition for Smart Transmit Power Control: 692 * 693 * This is the normal power setting used for frames that do not fall. 694 */ 695 #define DWT_TX_POWER_BOOSTNORM_MASK 0x00000000UL 696 #define DWT_BOOSTNORM_MASK DWT_TX_POWER_BOOSTNORM_MASK 697 #define DWT_TX_POWER_BOOSTNORM_SHIFT 0 698 /* 699 * This value sets the power applied during transmission 700 * at the 6.8 Mbps data rate frames that are less than 0.5 ms duration 701 */ 702 #define DWT_TX_POWER_BOOSTP500_MASK 0x00000000UL 703 #define DWT_BOOSTP500_MASK DWT_TX_POWER_BOOSTP500_MASK 704 #define DWT_TX_POWER_BOOSTP500_SHIFT 8 705 /* 706 * This value sets the power applied during transmission 707 * at the 6.8 Mbps data rate frames that are less than 0.25 ms duration 708 */ 709 #define DWT_TX_POWER_BOOSTP250_MASK 0x00000000UL 710 #define DWT_BOOSTP250_MASK DWT_TX_POWER_BOOSTP250_MASK 711 #define DWT_TX_POWER_BOOSTP250_SHIFT 16 712 /* 713 * This value sets the power applied during transmission 714 * at the 6.8 Mbps data rate frames that are less than 0.125 ms 715 */ 716 #define DWT_TX_POWER_BOOSTP125_MASK 0x00000000UL 717 #define DWT_BOOSTP125_MASK DWT_TX_POWER_BOOSTP125_MASK 718 #define DWT_TX_POWER_BOOSTP125_SHIFT 24 719 /* 720 * Mask and shift definition for Manual Transmit Power Control 721 * (DIS_STXP=1 in SYS_CFG) 722 */ 723 #define DWT_TX_POWER_MAN_DEFAULT 0x0E080222UL 724 /* 725 * This power setting is applied during the transmission 726 * of the PHY header (PHR) portion of the frame. 727 */ 728 #define DWT_TX_POWER_TXPOWPHR_MASK 0x0000FF00UL 729 /* 730 * This power setting is applied during the transmission 731 * of the synchronisation header (SHR) and data portions of the frame. 732 */ 733 #define DWT_TX_POWER_TXPOWSD_MASK 0x00FF0000UL 734 735 /* Channel Control */ 736 #define DWT_CHAN_CTRL_ID 0x1F 737 #define DWT_CHAN_CTRL_LEN 4 738 /* Channel Control Register access mask */ 739 #define DWT_CHAN_CTRL_MASK 0xFFFF00FFUL 740 /* Supported channels are 1, 2, 3, 4, 5, and 7. */ 741 #define DWT_CHAN_CTRL_TX_CHAN_MASK 0x0000000FUL 742 /* Bits 0..3 TX channel number 0-15 selection */ 743 #define DWT_CHAN_CTRL_TX_CHAN_SHIFT 0 744 #define DWT_CHAN_CTRL_RX_CHAN_MASK 0x000000F0UL 745 /* Bits 4..7 RX channel number 0-15 selection */ 746 #define DWT_CHAN_CTRL_RX_CHAN_SHIFT 4 747 /* 748 * Bits 18..19 Specify (Force) RX Pulse Repetition Rate: 749 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. 750 */ 751 #define DWT_CHAN_CTRL_RXFPRF_MASK 0x000C0000UL 752 #define DWT_CHAN_CTRL_RXFPRF_SHIFT 18 753 /* 754 * Specific RXFPRF configuration: 755 * 756 * Specify (Force) RX Pulse Repetition Rate: 757 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. 758 */ 759 #define DWT_CHAN_CTRL_RXFPRF_4 0x00000000UL 760 /* 761 * Specify (Force) RX Pulse Repetition Rate: 762 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. 763 */ 764 #define DWT_CHAN_CTRL_RXFPRF_16 0x00040000UL 765 /* 766 * Specify (Force) RX Pulse Repetition Rate: 767 * 00 = 4 MHz, 01 = 16 MHz, 10 = 64MHz. 768 */ 769 #define DWT_CHAN_CTRL_RXFPRF_64 0x00080000UL 770 /* Bits 22..26 TX Preamble Code selection, 1 to 24. */ 771 #define DWT_CHAN_CTRL_TX_PCOD_MASK 0x07C00000UL 772 #define DWT_CHAN_CTRL_TX_PCOD_SHIFT 22 773 /* Bits 27..31 RX Preamble Code selection, 1 to 24. */ 774 #define DWT_CHAN_CTRL_RX_PCOD_MASK 0xF8000000UL 775 #define DWT_CHAN_CTRL_RX_PCOD_SHIFT 27 776 /* Bit 17 This bit enables a non-standard DecaWave proprietary SFD sequence. */ 777 #define DWT_CHAN_CTRL_DWSFD 0x00020000UL 778 #define DWT_CHAN_CTRL_DWSFD_SHIFT 17 779 /* Bit 20 Non-standard SFD in the transmitter */ 780 #define DWT_CHAN_CTRL_TNSSFD 0x00100000UL 781 #define DWT_CHAN_CTRL_TNSSFD_SHIFT 20 782 /* Bit 21 Non-standard SFD in the receiver */ 783 #define DWT_CHAN_CTRL_RNSSFD 0x00200000UL 784 #define DWT_CHAN_CTRL_RNSSFD_SHIFT 21 785 786 #define DWT_REG_20_ID_RESERVED 0x20 787 788 /* User-specified short/long TX/RX SFD sequences */ 789 #define DWT_USR_SFD_ID 0x21 790 #define DWT_USR_SFD_LEN 41 791 /* Decawave non-standard SFD length for 110 kbps */ 792 #define DWT_DW_NS_SFD_LEN_110K 64 793 /* Decawave non-standard SFD length for 850 kbps */ 794 #define DWT_DW_NS_SFD_LEN_850K 16 795 /* Decawave non-standard SFD length for 6.8 Mbps */ 796 #define DWT_DW_NS_SFD_LEN_6M8 8 797 798 #define DWT_REG_22_ID_RESERVED 0x22 799 800 /* Automatic Gain Control configuration */ 801 #define DWT_AGC_CTRL_ID 0x23 802 #define DWT_AGC_CTRL_LEN 32 803 #define DWT_AGC_CFG_STS_ID DWT_AGC_CTRL_ID 804 #define DWT_AGC_CTRL1_OFFSET (0x02) 805 #define DWT_AGC_CTRL1_LEN 2 806 /* Access mask to AGC configuration and control register */ 807 #define DWT_AGC_CTRL1_MASK 0x0001 808 /* Disable AGC Measurement. The DIS_AM bit is set by default. */ 809 #define DWT_AGC_CTRL1_DIS_AM 0x0001 810 /* 811 * Offset from AGC_CTRL_ID in bytes. 812 * Please take care not to write other values to this register as doing so 813 * may cause the DW1000 to malfunction 814 */ 815 #define DWT_AGC_TUNE1_OFFSET (0x04) 816 #define DWT_AGC_TUNE1_LEN 2 817 /* It is a 16-bit tuning register for the AGC. */ 818 #define DWT_AGC_TUNE1_MASK 0xFFFF 819 #define DWT_AGC_TUNE1_16M 0x8870 820 #define DWT_AGC_TUNE1_64M 0x889B 821 /* 822 * Offset from AGC_CTRL_ID in bytes. 823 * Please take care not to write other values to this register as doing so 824 * may cause the DW1000 to malfunction 825 */ 826 #define DWT_AGC_TUNE2_OFFSET (0x0C) 827 #define DWT_AGC_TUNE2_LEN 4 828 #define DWT_AGC_TUNE2_MASK 0xFFFFFFFFUL 829 #define DWT_AGC_TUNE2_VAL 0X2502A907UL 830 /* 831 * Offset from AGC_CTRL_ID in bytes. 832 * Please take care not to write other values to this register as doing so 833 * may cause the DW1000 to malfunction 834 */ 835 #define DWT_AGC_TUNE3_LEN 2 836 #define DWT_AGC_TUNE3_MASK 0xFFFF 837 #define DWT_AGC_TUNE3_VAL 0X0055 838 #define DWT_AGC_STAT1_OFFSET (0x1E) 839 #define DWT_AGC_STAT1_LEN 3 840 #define DWT_AGC_STAT1_MASK 0x0FFFFF 841 /* This 5-bit gain value relates to input noise power measurement. */ 842 #define DWT_AGC_STAT1_EDG1_MASK 0x0007C0 843 /* This 9-bit value relates to the input noise power measurement. */ 844 #define DWT_AGC_STAT1_EDG2_MASK 0x0FF800 845 846 /* External synchronisation control */ 847 #define DWT_EXT_SYNC_ID 0x24 848 #define DWT_EXT_SYNC_LEN 12 849 #define DWT_EC_CTRL_OFFSET (0x00) 850 #define DWT_EC_CTRL_LEN 4 851 /* 852 * Sub-register 0x00 is the External clock synchronisation counter 853 * configuration register 854 */ 855 #define DWT_EC_CTRL_MASK 0x00000FFBUL 856 /* External transmit synchronisation mode enable */ 857 #define DWT_EC_CTRL_OSTSM 0x00000001UL 858 /* External receive synchronisation mode enable */ 859 #define DWT_EC_CTRL_OSRSM 0x00000002UL 860 /* PLL lock detect enable */ 861 #define DWT_EC_CTRL_PLLLCK 0x04 862 /* External timebase reset mode enable */ 863 #define DWT_EC_CTRL_OSTRM 0x00000800UL 864 /* 865 * Wait counter used for external transmit synchronisation and 866 * external timebase reset 867 */ 868 #define DWT_EC_CTRL_WAIT_MASK 0x000007F8UL 869 #define DWT_EC_RXTC_OFFSET (0x04) 870 #define DWT_EC_RXTC_LEN 4 871 /* External clock synchronisation counter captured on RMARKER */ 872 #define DWT_EC_RXTC_MASK 0xFFFFFFFFUL 873 #define DWT_EC_GOLP (0x08) 874 #define DWT_EC_GOLP_LEN 4 875 /* 876 * Sub-register 0x08 is the External clock offset to first path 1 GHz counter, 877 * EC_GOLP 878 */ 879 #define DWT_EC_GOLP_MASK 0x0000003FUL 880 /* 881 * This register contains the 1 GHz count from the arrival of the RMARKER and 882 * the next edge of the external clock. 883 */ 884 #define DWT_EC_GOLP_OFFSET_EXT_MASK 0x0000003FUL 885 886 /* Read access to accumulator data */ 887 #define DWT_ACC_MEM_ID 0x25 888 #define DWT_ACC_MEM_LEN 4064 889 890 /* Peripheral register bus 1 access - GPIO control */ 891 #define DWT_GPIO_CTRL_ID 0x26 892 #define DWT_GPIO_CTRL_LEN 44 893 894 /* Sub-register 0x00 is the GPIO Mode Control Register */ 895 #define DWT_GPIO_MODE_OFFSET 0x00 896 #define DWT_GPIO_MODE_LEN 4 897 #define DWT_GPIO_MODE_MASK 0x00FFFFC0UL 898 899 /* Mode Selection for GPIO0/RXOKLED */ 900 #define DWT_GPIO_MSGP0_MASK 0x000000C0UL 901 /* Mode Selection for GPIO1/SFDLED */ 902 #define DWT_GPIO_MSGP1_MASK 0x00000300UL 903 /* Mode Selection for GPIO2/RXLED */ 904 #define DWT_GPIO_MSGP2_MASK 0x00000C00UL 905 /* Mode Selection for GPIO3/TXLED */ 906 #define DWT_GPIO_MSGP3_MASK 0x00003000UL 907 /* Mode Selection for GPIO4/EXTPA */ 908 #define DWT_GPIO_MSGP4_MASK 0x0000C000UL 909 /* Mode Selection for GPIO5/EXTTXE */ 910 #define DWT_GPIO_MSGP5_MASK 0x00030000UL 911 /* Mode Selection for GPIO6/EXTRXE */ 912 #define DWT_GPIO_MSGP6_MASK 0x000C0000UL 913 /* Mode Selection for SYNC/GPIO7 */ 914 #define DWT_GPIO_MSGP7_MASK 0x00300000UL 915 /* Mode Selection for IRQ/GPIO8 */ 916 #define DWT_GPIO_MSGP8_MASK 0x00C00000UL 917 918 /* The pin operates as the RXLED output */ 919 #define DWT_GPIO_PIN2_RXLED 0x00000400UL 920 /* The pin operates as the TXLED output */ 921 #define DWT_GPIO_PIN3_TXLED 0x00001000UL 922 /* The pin operates as the EXTPA output */ 923 #define DWT_GPIO_PIN4_EXTPA 0x00004000UL 924 /* The pin operates as the EXTTXE output */ 925 #define DWT_GPIO_PIN5_EXTTXE 0x00010000UL 926 /* The pin operates as the EXTRXE output */ 927 #define DWT_GPIO_PIN6_EXTRXE 0x00040000UL 928 929 /* Sub-register 0x08 is the GPIO Direction Control Register */ 930 #define DWT_GPIO_DIR_OFFSET 0x08 931 #define DWT_GPIO_DIR_LEN 3 932 #define DWT_GPIO_DIR_MASK 0x0011FFFFUL 933 934 /* 935 * GPIO0 only changed if the GxM0 mask bit has a value of 1 936 * for the write operation 937 */ 938 #define DWT_GxP0 0x00000001UL 939 /* GPIO1. (See GDP0). */ 940 #define DWT_GxP1 0x00000002UL 941 /* GPIO2. (See GDP0). */ 942 #define DWT_GxP2 0x00000004UL 943 /* GPIO3. (See GDP0). */ 944 #define DWT_GxP3 0x00000008UL 945 /* GPIO4. (See GDP0). */ 946 #define DWT_GxP4 0x00000100UL 947 /* GPIO5. (See GDP0). */ 948 #define DWT_GxP5 0x00000200UL 949 /* GPIO6. (See GDP0). */ 950 #define DWT_GxP6 0x00000400UL 951 /* GPIO7. (See GDP0). */ 952 #define DWT_GxP7 0x00000800UL 953 /* GPIO8 */ 954 #define DWT_GxP8 0x00010000UL 955 956 /* Mask for GPIO0 */ 957 #define DWT_GxM0 0x00000010UL 958 /* Mask for GPIO1. (See GDM0). */ 959 #define DWT_GxM1 0x00000020UL 960 /* Mask for GPIO2. (See GDM0). */ 961 #define DWT_GxM2 0x00000040UL 962 /* Mask for GPIO3. (See GDM0). */ 963 #define DWT_GxM3 0x00000080UL 964 /* Mask for GPIO4. (See GDM0). */ 965 #define DWT_GxM4 0x00001000UL 966 /* Mask for GPIO5. (See GDM0). */ 967 #define DWT_GxM5 0x00002000UL 968 /* Mask for GPIO6. (See GDM0). */ 969 #define DWT_GxM6 0x00004000UL 970 /* Mask for GPIO7. (See GDM0). */ 971 #define DWT_GxM7 0x00008000UL 972 /* Mask for GPIO8. (See GDM0). */ 973 #define DWT_GxM8 0x00100000UL 974 975 /* 976 * Direction Selection for GPIO0. 1 = input, 0 = output. 977 * Only changed if the GDM0 mask bit has a value of 1 for the write operation 978 */ 979 #define DWT_GDP0 GxP0 980 /* Direction Selection for GPIO1. (See GDP0). */ 981 #define DWT_GDP1 GxP1 982 /* Direction Selection for GPIO2. (See GDP0). */ 983 #define DWT_GDP2 GxP2 984 /* Direction Selection for GPIO3. (See GDP0). */ 985 #define DWT_GDP3 GxP3 986 /* Direction Selection for GPIO4. (See GDP0). */ 987 #define DWT_GDP4 GxP4 988 /* Direction Selection for GPIO5. (See GDP0). */ 989 #define DWT_GDP5 GxP5 990 /* Direction Selection for GPIO6. (See GDP0). */ 991 #define DWT_GDP6 GxP6 992 /* Direction Selection for GPIO7. (See GDP0). */ 993 #define DWT_GDP7 GxP7 994 /* Direction Selection for GPIO8 */ 995 #define DWT_GDP8 GxP8 996 997 /* Mask for setting the direction of GPIO0 */ 998 #define DWT_GDM0 GxM0 999 /* Mask for setting the direction of GPIO1. (See GDM0). */ 1000 #define DWT_GDM1 GxM1 1001 /* Mask for setting the direction of GPIO2. (See GDM0). */ 1002 #define DWT_GDM2 GxM2 1003 /* Mask for setting the direction of GPIO3. (See GDM0). */ 1004 #define DWT_GDM3 GxM3 1005 /* Mask for setting the direction of GPIO4. (See GDM0). */ 1006 #define DWT_GDM4 GxM4 1007 /* Mask for setting the direction of GPIO5. (See GDM0). */ 1008 #define DWT_GDM5 GxM5 1009 /* Mask for setting the direction of GPIO6. (See GDM0). */ 1010 #define DWT_GDM6 GxM6 1011 /* Mask for setting the direction of GPIO7. (See GDM0). */ 1012 #define DWT_GDM7 GxM7 1013 /* Mask for setting the direction of GPIO8. (See GDM0). */ 1014 #define DWT_GDM8 GxM8 1015 1016 /* Sub-register 0x0C is the GPIO data output register. */ 1017 #define DWT_GPIO_DOUT_OFFSET 0x0C 1018 #define DWT_GPIO_DOUT_LEN 3 1019 #define DWT_GPIO_DOUT_MASK DWT_GPIO_DIR_MASK 1020 1021 /* Sub-register 0x10 is the GPIO interrupt enable register */ 1022 #define DWT_GPIO_IRQE_OFFSET 0x10 1023 #define DWT_GPIO_IRQE_LEN 4 1024 #define DWT_GPIO_IRQE_MASK 0x000001FFUL 1025 /* IRQ bit0 */ 1026 #define DWT_GIRQx0 0x00000001UL 1027 /* IRQ bit1 */ 1028 #define DWT_GIRQx1 0x00000002UL 1029 /* IRQ bit2 */ 1030 #define DWT_GIRQx2 0x00000004UL 1031 /* IRQ bit3 */ 1032 #define DWT_GIRQx3 0x00000008UL 1033 /* IRQ bit4 */ 1034 #define DWT_GIRQx4 0x00000010UL 1035 /* IRQ bit5 */ 1036 #define DWT_GIRQx5 0x00000020UL 1037 /* IRQ bit6 */ 1038 #define DWT_GIRQx6 0x00000040UL 1039 /* IRQ bit7 */ 1040 #define DWT_GIRQx7 0x00000080UL 1041 /* IRQ bit8 */ 1042 #define DWT_GIRQx8 0x00000100UL 1043 /* GPIO IRQ Enable for GPIO0 input. Value 1 = enable, 0 = disable */ 1044 #define DWT_GIRQE0 GIRQx0 1045 #define DWT_GIRQE1 GIRQx1 1046 #define DWT_GIRQE2 GIRQx2 1047 #define DWT_GIRQE3 GIRQx3 1048 #define DWT_GIRQE4 GIRQx4 1049 #define DWT_GIRQE5 GIRQx5 1050 #define DWT_GIRQE6 GIRQx6 1051 #define DWT_GIRQE7 GIRQx7 1052 #define DWT_GIRQE8 GIRQx8 1053 1054 /* Sub-register 0x14 is the GPIO interrupt sense selection register */ 1055 #define DWT_GPIO_ISEN_OFFSET 0x14 1056 #define DWT_GPIO_ISEN_LEN 4 1057 #define DWT_GPIO_ISEN_MASK DWT_GPIO_IRQE_MASK 1058 /* GPIO IRQ Sense selection GPIO0 input. 1059 * Value 0 = High or Rising-Edge, 1060 * 1 = Low or falling-edge. 1061 */ 1062 #define DWT_GISEN0 GIRQx0 1063 #define DWT_GISEN1 GIRQx1 1064 #define DWT_GISEN2 GIRQx2 1065 #define DWT_GISEN3 GIRQx3 1066 #define DWT_GISEN4 GIRQx4 1067 #define DWT_GISEN5 GIRQx5 1068 #define DWT_GISEN6 GIRQx6 1069 #define DWT_GISEN7 GIRQx7 1070 #define DWT_GISEN8 GIRQx8 1071 1072 /* Sub-register 0x18 is the GPIO interrupt mode selection register */ 1073 #define DWT_GPIO_IMODE_OFFSET 0x18 1074 #define DWT_GPIO_IMODE_LEN 4 1075 #define DWT_GPIO_IMODE_MASK DWT_GPIO_IRQE_MASK 1076 /* GPIO IRQ Mode selection for GPIO0 input. 1077 * Value 0 = Level sensitive interrupt. 1078 * Value 1 = Edge triggered interrupt 1079 */ 1080 #define DWT_GIMOD0 GIRQx0 1081 #define DWT_GIMOD1 GIRQx1 1082 #define DWT_GIMOD2 GIRQx2 1083 #define DWT_GIMOD3 GIRQx3 1084 #define DWT_GIMOD4 GIRQx4 1085 #define DWT_GIMOD5 GIRQx5 1086 #define DWT_GIMOD6 GIRQx6 1087 #define DWT_GIMOD7 GIRQx7 1088 #define DWT_GIMOD8 GIRQx8 1089 1090 /* Sub-register 0x1C is the GPIO interrupt "Both Edge" selection register */ 1091 #define DWT_GPIO_IBES_OFFSET 0x1C 1092 #define DWT_GPIO_IBES_LEN 4 1093 #define DWT_GPIO_IBES_MASK DWT_GPIO_IRQE_MASK 1094 /* GPIO IRQ "Both Edge" selection for GPIO0 input. 1095 * Value 0 = GPIO_IMODE register selects the edge. 1096 * Value 1 = Both edges trigger the interrupt. 1097 */ 1098 #define DWT_GIBES0 GIRQx0 1099 #define DWT_GIBES1 GIRQx1 1100 #define DWT_GIBES2 GIRQx2 1101 #define DWT_GIBES3 GIRQx3 1102 #define DWT_GIBES4 GIRQx4 1103 #define DWT_GIBES5 GIRQx5 1104 #define DWT_GIBES6 GIRQx6 1105 #define DWT_GIBES7 GIRQx7 1106 #define DWT_GIBES8 GIRQx8 1107 1108 /* Sub-register 0x20 is the GPIO interrupt clear register */ 1109 #define DWT_GPIO_ICLR_OFFSET 0x20 1110 #define DWT_GPIO_ICLR_LEN 4 1111 #define DWT_GPIO_ICLR_MASK DWT_GPIO_IRQE_MASK 1112 /* GPIO IRQ latch clear for GPIO0 input. 1113 * Write 1 to clear the GPIO0 interrupt latch. 1114 * Writing 0 has no effect. Reading returns zero 1115 */ 1116 #define DWT_GICLR0 GIRQx0 1117 #define DWT_GICLR1 GIRQx1 1118 #define DWT_GICLR2 GIRQx2 1119 #define DWT_GICLR3 GIRQx3 1120 #define DWT_GICLR4 GIRQx4 1121 #define DWT_GICLR5 GIRQx5 1122 #define DWT_GICLR6 GIRQx6 1123 #define DWT_GICLR7 GIRQx7 1124 #define DWT_GICLR8 GIRQx8 1125 1126 /* Sub-register 0x24 is the GPIO interrupt de-bounce enable register */ 1127 #define DWT_GPIO_IDBE_OFFSET 0x24 1128 #define DWT_GPIO_IDBE_LEN 4 1129 #define DWT_GPIO_IDBE_MASK DWT_GPIO_IRQE_MASK 1130 /* GPIO IRQ de-bounce enable for GPIO0. 1131 * Value 1 = de-bounce enabled. 1132 * Value 0 = de-bounce disabled 1133 */ 1134 #define DWT_GIDBE0 GIRQx0 1135 #define DWT_GIDBE1 GIRQx1 1136 #define DWT_GIDBE2 GIRQx2 1137 #define DWT_GIDBE3 GIRQx3 1138 #define DWT_GIDBE4 GIRQx4 1139 #define DWT_GIDBE5 GIRQx5 1140 #define DWT_GIDBE6 GIRQx6 1141 #define DWT_GIDBE7 GIRQx7 1142 /* Value 1 = de-bounce enabled, 0 = de-bounce disabled */ 1143 #define DWT_GIDBE8 GIRQx8 1144 1145 /* Sub-register 0x28 allows the raw state of the GPIO pin to be read. */ 1146 #define DWT_GPIO_RAW_OFFSET 0x28 1147 #define DWT_GPIO_RAW_LEN 4 1148 #define DWT_GPIO_RAW_MASK DWT_GPIO_IRQE_MASK 1149 /* This bit reflects the raw state of GPIO0 .. GPIO8 */ 1150 #define DWT_GRAWP0 GIRQx0 1151 #define DWT_GRAWP1 GIRQx1 1152 #define DWT_GRAWP2 GIRQx2 1153 #define DWT_GRAWP3 GIRQx3 1154 #define DWT_GRAWP4 GIRQx4 1155 #define DWT_GRAWP5 GIRQx5 1156 #define DWT_GRAWP6 GIRQx6 1157 #define DWT_GRAWP7 GIRQx7 1158 #define DWT_GRAWP8 GIRQx8 1159 1160 /* Digital Receiver configuration */ 1161 #define DWT_DRX_CONF_ID 0x27 1162 #define DWT_DRX_CONF_LEN 44 1163 /* Sub-register 0x02 is a 16-bit tuning register. */ 1164 #define DWT_DRX_TUNE0b_OFFSET (0x02) 1165 #define DWT_DRX_TUNE0b_LEN 2 1166 /* 7.2.40.2 Sub-Register 0x27:02 DRX_TUNE0b */ 1167 #define DWT_DRX_TUNE0b_MASK 0xFFFF 1168 #define DWT_DRX_TUNE0b_110K_STD 0x000A 1169 #define DWT_DRX_TUNE0b_110K_NSTD 0x0016 1170 #define DWT_DRX_TUNE0b_850K_STD 0x0001 1171 #define DWT_DRX_TUNE0b_850K_NSTD 0x0006 1172 #define DWT_DRX_TUNE0b_6M8_STD 0x0001 1173 #define DWT_DRX_TUNE0b_6M8_NSTD 0x0002 1174 1175 /* 7.2.40.3 Sub-Register 0x27:04 DRX_TUNE1a */ 1176 #define DWT_DRX_TUNE1a_OFFSET 0x04 1177 #define DWT_DRX_TUNE1a_LEN 2 1178 #define DWT_DRX_TUNE1a_MASK 0xFFFF 1179 #define DWT_DRX_TUNE1a_PRF16 0x0087 1180 #define DWT_DRX_TUNE1a_PRF64 0x008D 1181 1182 /* 7.2.40.4 Sub-Register 0x27:06 DRX_TUNE1b */ 1183 #define DWT_DRX_TUNE1b_OFFSET 0x06 1184 #define DWT_DRX_TUNE1b_LEN 2 1185 #define DWT_DRX_TUNE1b_MASK 0xFFFF 1186 #define DWT_DRX_TUNE1b_110K 0x0064 1187 #define DWT_DRX_TUNE1b_850K_6M8 0x0020 1188 #define DWT_DRX_TUNE1b_6M8_PRE64 0x0010 1189 1190 /* 7.2.40.5 Sub-Register 0x27:08 DRX_TUNE2 */ 1191 #define DWT_DRX_TUNE2_OFFSET 0x08 1192 #define DWT_DRX_TUNE2_LEN 4 1193 #define DWT_DRX_TUNE2_MASK 0xFFFFFFFFUL 1194 #define DWT_DRX_TUNE2_PRF16_PAC8 0x311A002DUL 1195 #define DWT_DRX_TUNE2_PRF16_PAC16 0x331A0052UL 1196 #define DWT_DRX_TUNE2_PRF16_PAC32 0x351A009AUL 1197 #define DWT_DRX_TUNE2_PRF16_PAC64 0x371A011DUL 1198 #define DWT_DRX_TUNE2_PRF64_PAC8 0x313B006BUL 1199 #define DWT_DRX_TUNE2_PRF64_PAC16 0x333B00BEUL 1200 #define DWT_DRX_TUNE2_PRF64_PAC32 0x353B015EUL 1201 #define DWT_DRX_TUNE2_PRF64_PAC64 0x373B0296UL 1202 1203 /* WARNING: Please do NOT set DRX_SFDTOC to zero 1204 * (disabling SFD detection timeout) since this risks IC malfunction 1205 * due to prolonged receiver activity in the event of false preamble detection. 1206 */ 1207 /* 7.2.40.7 Sub-Register 0x27:20 DRX_SFDTOC */ 1208 #define DWT_DRX_SFDTOC_OFFSET 0x20 1209 #define DWT_DRX_SFDTOC_LEN 2 1210 #define DWT_DRX_SFDTOC_MASK 0xFFFF 1211 1212 /* 7.2.40.9 Sub-Register 0x27:24 DRX_PRETOC */ 1213 #define DWT_DRX_PRETOC_OFFSET 0x24 1214 #define DWT_DRX_PRETOC_LEN 2 1215 #define DWT_DRX_PRETOC_MASK 0xFFFF 1216 1217 /* 7.2.40.10 Sub-Register 0x27:26 DRX_TUNE4H */ 1218 #define DWT_DRX_TUNE4H_OFFSET 0x26 1219 #define DWT_DRX_TUNE4H_LEN 2 1220 #define DWT_DRX_TUNE4H_MASK 0xFFFF 1221 #define DWT_DRX_TUNE4H_PRE64 0x0010 1222 #define DWT_DRX_TUNE4H_PRE128PLUS 0x0028 1223 1224 /* 1225 * Offset from DRX_CONF_ID in bytes to 21-bit signed 1226 * RX carrier integrator value 1227 */ 1228 #define DWT_DRX_CARRIER_INT_OFFSET 0x28 1229 #define DWT_DRX_CARRIER_INT_LEN 3 1230 #define DWT_DRX_CARRIER_INT_MASK 0x001FFFFF 1231 1232 /* 7.2.40.11 Sub-Register 0x27:2C - RXPACC_NOSAT */ 1233 #define DWT_RPACC_NOSAT_OFFSET 0x2C 1234 #define DWT_RPACC_NOSAT_LEN 2 1235 #define DWT_RPACC_NOSAT_MASK 0xFFFF 1236 1237 /* Analog RF Configuration */ 1238 #define DWT_RF_CONF_ID 0x28 1239 #define DWT_RF_CONF_LEN 58 1240 /* TX enable */ 1241 #define DWT_RF_CONF_TXEN_MASK 0x00400000UL 1242 /* RX enable */ 1243 #define DWT_RF_CONF_RXEN_MASK 0x00200000UL 1244 /* Turn on power all LDOs */ 1245 #define DWT_RF_CONF_TXPOW_MASK 0x001F0000UL 1246 /* Enable PLLs */ 1247 #define DWT_RF_CONF_PLLEN_MASK 0x0000E000UL 1248 /* Enable TX blocks */ 1249 #define DWT_RF_CONF_TXBLOCKSEN_MASK 0x00001F00UL 1250 #define DWT_RF_CONF_TXPLLPOWEN_MASK (DWT_RF_CONF_PLLEN_MASK | \ 1251 DWT_RF_CONF_TXPOW_MASK) 1252 #define DWT_RF_CONF_TXALLEN_MASK (DWT_RF_CONF_TXEN_MASK | \ 1253 DWT_RF_CONF_TXPOW_MASK | \ 1254 DWT_RF_CONF_PLLEN_MASK | \ 1255 DWT_RF_CONF_TXBLOCKSEN_MASK) 1256 /* Analog RX Control Register */ 1257 #define DWT_RF_RXCTRLH_OFFSET 0x0B 1258 #define DWT_RF_RXCTRLH_LEN 1 1259 /* RXCTRLH value for narrow bandwidth channels */ 1260 #define DWT_RF_RXCTRLH_NBW 0xD8 1261 /* RXCTRLH value for wide bandwidth channels */ 1262 #define DWT_RF_RXCTRLH_WBW 0xBC 1263 /* Analog TX Control Register */ 1264 #define DWT_RF_TXCTRL_OFFSET 0x0C 1265 #define DWT_RF_TXCTRL_LEN 4 1266 /* Transmit mixer tuning register */ 1267 #define DWT_RF_TXCTRL_TXMTUNE_MASK 0x000001E0UL 1268 /* Transmit mixer Q-factor tuning register */ 1269 #define DWT_RF_TXCTRL_TXTXMQ_MASK 0x00000E00UL 1270 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ 1271 #define DWT_RF_TXCTRL_CH1 0x00005C40UL 1272 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ 1273 #define DWT_RF_TXCTRL_CH2 0x00045CA0UL 1274 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ 1275 #define DWT_RF_TXCTRL_CH3 0x00086CC0UL 1276 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ 1277 #define DWT_RF_TXCTRL_CH4 0x00045C80UL 1278 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ 1279 #define DWT_RF_TXCTRL_CH5 0x001E3FE0UL 1280 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */ 1281 #define DWT_RF_TXCTRL_CH7 0x001E7DE0UL 1282 1283 #define DWT_RF_STATUS_OFFSET 0x2C 1284 1285 #define DWT_REG_29_ID_RESERVED 0x29 1286 1287 /* Transmitter calibration block */ 1288 #define DWT_TX_CAL_ID 0x2A 1289 #define DWT_TX_CAL_LEN 52 1290 /* SAR control */ 1291 #define DWT_TC_SARL_SAR_C 0 1292 /* Cause bug in register block TX_CAL, we need to read 1 byte in a time */ 1293 /* Latest SAR reading for Voltage level */ 1294 #define DWT_TC_SARL_SAR_LVBAT_OFFSET 3 1295 /* Latest SAR reading for Temperature level */ 1296 #define DWT_TC_SARL_SAR_LTEMP_OFFSET 4 1297 /* SAR reading of Temperature level taken at last wakeup event */ 1298 #define DWT_TC_SARW_SAR_WTEMP_OFFSET 0x06 1299 /* SAR reading of Voltage level taken at last wakeup event */ 1300 #define DWT_TC_SARW_SAR_WVBAT_OFFSET 0x07 1301 /* Transmitter Calibration Pulse Generator Delay */ 1302 #define DWT_TC_PGDELAY_OFFSET 0x0B 1303 #define DWT_TC_PGDELAY_LEN 1 1304 /* Recommended value for channel 1 */ 1305 #define DWT_TC_PGDELAY_CH1 0xC9 1306 /* Recommended value for channel 2 */ 1307 #define DWT_TC_PGDELAY_CH2 0xC2 1308 /* Recommended value for channel 3 */ 1309 #define DWT_TC_PGDELAY_CH3 0xC5 1310 /* Recommended value for channel 4 */ 1311 #define DWT_TC_PGDELAY_CH4 0x95 1312 /* Recommended value for channel 5 */ 1313 #define DWT_TC_PGDELAY_CH5 0xC0 1314 /* Recommended value for channel 7 */ 1315 #define DWT_TC_PGDELAY_CH7 0x93 1316 /* Transmitter Calibration Pulse Generator Test */ 1317 #define DWT_TC_PGTEST_OFFSET 0x0C 1318 #define DWT_TC_PGTEST_LEN 1 1319 /* Normal operation */ 1320 #define DWT_TC_PGTEST_NORMAL 0x00 1321 /* Continuous Wave (CW) Test Mode */ 1322 #define DWT_TC_PGTEST_CW 0x13 1323 1324 /* Frequency synthesiser control block */ 1325 #define DWT_FS_CTRL_ID 0x2B 1326 #define DWT_FS_CTRL_LEN 21 1327 /* 1328 * Offset from FS_CTRL_ID in bytes, reserved area. 1329 * Please take care not to write to this area as doing so 1330 * may cause the DW1000 to malfunction. 1331 */ 1332 #define DWT_FS_RES1_OFFSET 0x00 1333 #define DWT_FS_RES1_LEN 7 1334 /* Frequency synthesiser PLL configuration */ 1335 #define DWT_FS_PLLCFG_OFFSET 0x07 1336 #define DWT_FS_PLLCFG_LEN 5 1337 /* Operating Channel 1 */ 1338 #define DWT_FS_PLLCFG_CH1 0x09000407UL 1339 /* Operating Channel 2 */ 1340 #define DWT_FS_PLLCFG_CH2 0x08400508UL 1341 /* Operating Channel 3 */ 1342 #define DWT_FS_PLLCFG_CH3 0x08401009UL 1343 /* Operating Channel 4 (same as 2) */ 1344 #define DWT_FS_PLLCFG_CH4 DWT_FS_PLLCFG_CH2 1345 /* Operating Channel 5 */ 1346 #define DWT_FS_PLLCFG_CH5 0x0800041DUL 1347 /* Operating Channel 7 (same as 5) */ 1348 #define DWT_FS_PLLCFG_CH7 DWT_FS_PLLCFG_CH5 1349 /* Frequency synthesiser PLL Tuning */ 1350 #define DWT_FS_PLLTUNE_OFFSET 0x0B 1351 #define DWT_FS_PLLTUNE_LEN 1 1352 /* Operating Channel 1 */ 1353 #define DWT_FS_PLLTUNE_CH1 0x1E 1354 /* Operating Channel 2 */ 1355 #define DWT_FS_PLLTUNE_CH2 0x26 1356 /* Operating Channel 3 */ 1357 #define DWT_FS_PLLTUNE_CH3 0x56 1358 /* Operating Channel 4 (same as 2) */ 1359 #define DWT_FS_PLLTUNE_CH4 DWT_FS_PLLTUNE_CH2 1360 /* Operating Channel 5 */ 1361 #define DWT_FS_PLLTUNE_CH5 0xBE 1362 /* Operating Channel 7 (same as 5) */ 1363 #define DWT_FS_PLLTUNE_CH7 DWT_FS_PLLTUNE_CH5 1364 /* 1365 * Offset from FS_CTRL_ID in bytes. 1366 * Please take care not to write to this area as doing so 1367 * may cause the DW1000 to malfunction. 1368 */ 1369 #define DWT_FS_RES2_OFFSET 0x0C 1370 #define DWT_FS_RES2_LEN 2 1371 /* Frequency synthesiser Crystal trim */ 1372 #define DWT_FS_XTALT_OFFSET 0x0E 1373 #define DWT_FS_XTALT_LEN 1 1374 /* 1375 * Crystal Trim. 1376 * Crystals may be trimmed using this register setting to tune out errors, 1377 * see 8.1 IC Calibration Crystal Oscillator Trim. 1378 */ 1379 #define DWT_FS_XTALT_MASK 0x1F 1380 #define DWT_FS_XTALT_MIDRANGE 0x10 1381 /* 1382 * Offset from FS_CTRL_ID in bytes. 1383 * Please take care not to write to this area as doing so 1384 * may cause the DW1000 to malfunction. 1385 */ 1386 #define DWT_FS_RES3_OFFSET 0x0F 1387 #define DWT_FS_RES3_LEN 6 1388 1389 /* Always-On register set */ 1390 #define DWT_AON_ID 0x2C 1391 #define DWT_AON_LEN 12 1392 /* 1393 * Offset from AON_ID in bytes 1394 * Used to control what the DW1000 IC does as it wakes up from 1395 * low-power SLEEP or DEEPSLEEPstates. 1396 */ 1397 #define DWT_AON_WCFG_OFFSET 0x00 1398 #define DWT_AON_WCFG_LEN 2 1399 /* Access mask to AON_WCFG register */ 1400 #define DWT_AON_WCFG_MASK 0x09CB 1401 /* On Wake-up Run the (temperature and voltage) Analog-to-Digital Converters */ 1402 #define DWT_AON_WCFG_ONW_RADC 0x0001 1403 /* On Wake-up turn on the Receiver */ 1404 #define DWT_AON_WCFG_ONW_RX 0x0002 1405 /* 1406 * On Wake-up load the EUI from OTP memory into Register file: 1407 * 0x01 Extended Unique Identifier. 1408 */ 1409 #define DWT_AON_WCFG_ONW_LEUI 0x0008 1410 /* 1411 * On Wake-up load configurations from the AON memory 1412 * into the host interface register set 1413 */ 1414 #define DWT_AON_WCFG_ONW_LDC 0x0040 1415 /* On Wake-up load the Length64 receiver operating parameter set */ 1416 #define DWT_AON_WCFG_ONW_L64P 0x0080 1417 /* 1418 * Preserve Sleep. This bit determines what the DW1000 does 1419 * with respect to the ARXSLP and ATXSLP sleep controls 1420 */ 1421 #define DWT_AON_WCFG_PRES_SLEEP 0x0100 1422 /* On Wake-up load the LDE microcode. */ 1423 #define DWT_AON_WCFG_ONW_LLDE 0x0800 1424 /* On Wake-up load the LDO tune value. */ 1425 #define DWT_AON_WCFG_ONW_LLDO 0x1000 1426 /* 1427 * The bits in this register in general cause direct activity 1428 * within the AON block with respect to the stored AON memory 1429 */ 1430 #define DWT_AON_CTRL_OFFSET 0x02 1431 #define DWT_AON_CTRL_LEN 1 1432 /* Access mask to AON_CTRL register */ 1433 #define DWT_AON_CTRL_MASK 0x8F 1434 /* 1435 * When this bit is set the DW1000 will copy the user configurations 1436 * from the AON memory to the host interface register set. 1437 */ 1438 #define DWT_AON_CTRL_RESTORE 0x01 1439 /* 1440 * When this bit is set the DW1000 will copy the user configurations 1441 * from the host interface register set into the AON memory 1442 */ 1443 #define DWT_AON_CTRL_SAVE 0x02 1444 /* Upload the AON block configurations to the AON */ 1445 #define DWT_AON_CTRL_UPL_CFG 0x04 1446 /* Direct AON memory access read */ 1447 #define DWT_AON_CTRL_DCA_READ 0x08 1448 /* Direct AON memory access enable bit */ 1449 #define DWT_AON_CTRL_DCA_ENAB 0x80 1450 /* AON Direct Access Read Data Result */ 1451 #define DWT_AON_RDAT_OFFSET 0x03 1452 #define DWT_AON_RDAT_LEN 1 1453 /* AON Direct Access Address */ 1454 #define DWT_AON_ADDR_OFFSET 0x04 1455 #define DWT_AON_ADDR_LEN 1 1456 /* Address of low-power oscillator calibration value (lower byte) */ 1457 #define DWT_AON_ADDR_LPOSC_CAL_0 117 1458 /* Address of low-power oscillator calibration value (lower byte) */ 1459 #define DWT_AON_ADDR_LPOSC_CAL_1 118 1460 1461 /* 32-bit configuration register for the always on block. */ 1462 #define DWT_AON_CFG0_OFFSET 0x06 1463 #define DWT_AON_CFG0_LEN 4 1464 /* This is the sleep enable configuration bit */ 1465 #define DWT_AON_CFG0_SLEEP_EN 0x00000001UL 1466 /* Wake using WAKEUP pin */ 1467 #define DWT_AON_CFG0_WAKE_PIN 0x00000002UL 1468 /* Wake using SPI access SPICSn */ 1469 #define DWT_AON_CFG0_WAKE_SPI 0x00000004UL 1470 /* Wake when sleep counter elapses */ 1471 #define DWT_AON_CFG0_WAKE_CNT 0x00000008UL 1472 /* Low power divider enable configuration */ 1473 #define DWT_AON_CFG0_LPDIV_EN 0x00000010UL 1474 /* 1475 * Divider count for dividing the raw DW1000 XTAL oscillator frequency 1476 * to set an LP clock frequency 1477 */ 1478 #define DWT_AON_CFG0_LPCLKDIVA_MASK 0x0000FFE0UL 1479 #define DWT_AON_CFG0_LPCLKDIVA_SHIFT 5 1480 /* Sleep time. This field configures the sleep time count elapse value */ 1481 #define DWT_AON_CFG0_SLEEP_TIM 0xFFFF0000UL 1482 #define DWT_AON_CFG0_SLEEP_SHIFT 16 1483 #define DWT_AON_CFG0_SLEEP_TIM_OFFSET 2 1484 #define DWT_AON_CFG1_OFFSET 0x0A 1485 #define DWT_AON_CFG1_LEN 2 1486 /* access mask to AON_CFG1 */ 1487 #define DWT_AON_CFG1_MASK 0x0007 1488 /* This bit enables the sleep counter */ 1489 #define DWT_AON_CFG1_SLEEP_CEN 0x0001 1490 /* 1491 * This bit needs to be set to 0 for correct operation 1492 * in the SLEEP state within the DW1000 1493 */ 1494 #define DWT_AON_CFG1_SMXX 0x0002 1495 /* 1496 * This bit enables the calibration function that measures 1497 * the period of the ICs internal low powered oscillator. 1498 */ 1499 #define DWT_AON_CFG1_LPOSC_CAL 0x0004 1500 1501 /* One Time Programmable Memory Interface */ 1502 #define DWT_OTP_IF_ID 0x2D 1503 #define DWT_OTP_IF_LEN 18 1504 /* 32-bit register. The data value to be programmed into an OTP location */ 1505 #define DWT_OTP_WDAT 0x00 1506 #define DWT_OTP_WDAT_LEN 4 1507 /* 16-bit register used to select the address within the OTP memory block */ 1508 #define DWT_OTP_ADDR 0x04 1509 #define DWT_OTP_ADDR_LEN 2 1510 /* 1511 * This 11-bit field specifies the address within OTP memory 1512 * that will be accessed read or written. 1513 */ 1514 #define DWT_OTP_ADDR_MASK 0x07FF 1515 /* used to control the operation of the OTP memory */ 1516 #define DWT_OTP_CTRL 0x06 1517 #define DWT_OTP_CTRL_LEN 2 1518 #define DWT_OTP_CTRL_MASK 0x8002 1519 /* This bit forces the OTP into manual read mode */ 1520 #define DWT_OTP_CTRL_OTPRDEN 0x0001 1521 /* 1522 * This bit commands a read operation from the address specified 1523 * in the OTP_ADDR register 1524 */ 1525 #define DWT_OTP_CTRL_OTPREAD 0x0002 1526 /* This bit forces a load of LDE microcode */ 1527 #define DWT_OTP_CTRL_LDELOAD 0x8000 1528 /* 1529 * Setting this bit will cause the contents of OTP_WDAT to be written 1530 * to OTP_ADDR. 1531 */ 1532 #define DWT_OTP_CTRL_OTPPROG 0x0040 1533 #define DWT_OTP_STAT 0x08 1534 #define DWT_OTP_STAT_LEN 2 1535 #define DWT_OTP_STAT_MASK 0x0003 1536 /* OTP Programming Done */ 1537 #define DWT_OTP_STAT_OTPPRGD 0x0001 1538 /* OTP Programming Voltage OK */ 1539 #define DWT_OTP_STAT_OTPVPOK 0x0002 1540 /* 32-bit register. The data value read from an OTP location will appear here */ 1541 #define DWT_OTP_RDAT 0x0A 1542 #define DWT_OTP_RDAT_LEN 4 1543 /* 1544 * 32-bit register. The data value stored in the OTP SR (0x400) location 1545 * will appear here after power up 1546 */ 1547 #define DWT_OTP_SRDAT 0x0E 1548 #define DWT_OTP_SRDAT_LEN 4 1549 /* 1550 * 8-bit special function register used to select and 1551 * load special receiver operational parameter 1552 */ 1553 #define DWT_OTP_SF 0x12 1554 #define DWT_OTP_SF_LEN 1 1555 #define DWT_OTP_SF_MASK 0x63 1556 /* 1557 * This bit when set initiates a load of the operating parameter set 1558 * selected by the OPS_SEL 1559 */ 1560 #define DWT_OTP_SF_OPS_KICK 0x01 1561 /* This bit when set initiates a load of the LDO tune code */ 1562 #define DWT_OTP_SF_LDO_KICK 0x02 1563 #define DWT_OTP_SF_OPS_SEL_SHFT 5 1564 #define DWT_OTP_SF_OPS_SEL_MASK 0x60 1565 /* Operating parameter set selection: Length64 */ 1566 #define DWT_OTP_SF_OPS_SEL_L64 0x00 1567 /* Operating parameter set selection: Tight */ 1568 #define DWT_OTP_SF_OPS_SEL_TIGHT 0x40 1569 1570 /* Leading edge detection control block */ 1571 #define DWT_LDE_IF_ID 0x2E 1572 #define DWT_LDE_IF_LEN 0 1573 /* 1574 * 16-bit status register reporting the threshold that was used 1575 * to find the first path 1576 */ 1577 #define DWT_LDE_THRESH_OFFSET 0x0000 1578 #define DWT_LDE_THRESH_LEN 2 1579 /*8-bit configuration register */ 1580 #define DWT_LDE_CFG1_OFFSET 0x0806 1581 #define DWT_LDE_CFG1_LEN 1 1582 /* Number of Standard Deviations mask. */ 1583 #define DWT_LDE_CFG1_NSTDEV_MASK 0x1F 1584 /* Peak Multiplier mask. */ 1585 #define DWT_LDE_CFG1_PMULT_MASK 0xE0 1586 /* 1587 * Reporting the position within the accumulator that the LDE algorithm 1588 * has determined to contain the maximum 1589 */ 1590 #define DWT_LDE_PPINDX_OFFSET 0x1000 1591 #define DWT_LDE_PPINDX_LEN 2 1592 /* 1593 * Reporting the magnitude of the peak signal seen 1594 * in the accumulator data memory 1595 */ 1596 #define DWT_LDE_PPAMPL_OFFSET 0x1002 1597 #define DWT_LDE_PPAMPL_LEN 2 1598 /* 16-bit configuration register for setting the receive antenna delay */ 1599 #define DWT_LDE_RXANTD_OFFSET 0x1804 1600 #define DWT_LDE_RXANTD_LEN 2 1601 /* 16-bit LDE configuration tuning register */ 1602 #define DWT_LDE_CFG2_OFFSET 0x1806 1603 #define DWT_LDE_CFG2_LEN 2 1604 /* 1605 * 16-bit configuration register for setting 1606 * the replica avoidance coefficient 1607 */ 1608 #define DWT_LDE_REPC_OFFSET 0x2804 1609 #define DWT_LDE_REPC_LEN 2 1610 #define DWT_LDE_REPC_PCODE_1 0x5998 1611 #define DWT_LDE_REPC_PCODE_2 0x5998 1612 #define DWT_LDE_REPC_PCODE_3 0x51EA 1613 #define DWT_LDE_REPC_PCODE_4 0x428E 1614 #define DWT_LDE_REPC_PCODE_5 0x451E 1615 #define DWT_LDE_REPC_PCODE_6 0x2E14 1616 #define DWT_LDE_REPC_PCODE_7 0x8000 1617 #define DWT_LDE_REPC_PCODE_8 0x51EA 1618 #define DWT_LDE_REPC_PCODE_9 0x28F4 1619 #define DWT_LDE_REPC_PCODE_10 0x3332 1620 #define DWT_LDE_REPC_PCODE_11 0x3AE0 1621 #define DWT_LDE_REPC_PCODE_12 0x3D70 1622 #define DWT_LDE_REPC_PCODE_13 0x3AE0 1623 #define DWT_LDE_REPC_PCODE_14 0x35C2 1624 #define DWT_LDE_REPC_PCODE_15 0x2B84 1625 #define DWT_LDE_REPC_PCODE_16 0x35C2 1626 #define DWT_LDE_REPC_PCODE_17 0x3332 1627 #define DWT_LDE_REPC_PCODE_18 0x35C2 1628 #define DWT_LDE_REPC_PCODE_19 0x35C2 1629 #define DWT_LDE_REPC_PCODE_20 0x47AE 1630 #define DWT_LDE_REPC_PCODE_21 0x3AE0 1631 #define DWT_LDE_REPC_PCODE_22 0x3850 1632 #define DWT_LDE_REPC_PCODE_23 0x30A2 1633 #define DWT_LDE_REPC_PCODE_24 0x3850 1634 1635 /* Digital Diagnostics Interface */ 1636 #define DWT_DIG_DIAG_ID 0x2F 1637 #define DWT_DIG_DIAG_LEN 41 1638 1639 /* Event Counter Control */ 1640 #define DWT_EVC_CTRL_OFFSET 0x00 1641 #define DWT_EVC_CTRL_LEN 4 1642 /* 1643 * Access mask to Register for bits should always be set to zero 1644 * to avoid any malfunction of the device. 1645 */ 1646 #define DWT_EVC_CTRL_MASK 0x00000003UL 1647 /* Event Counters Enable bit */ 1648 #define DWT_EVC_EN 0x00000001UL 1649 #define DWT_EVC_CLR 0x00000002UL 1650 1651 /* PHR Error Event Counter */ 1652 #define DWT_EVC_PHE_OFFSET 0x04 1653 #define DWT_EVC_PHE_LEN 2 1654 #define DWT_EVC_PHE_MASK 0x0FFF 1655 /* Reed Solomon decoder (Frame Sync Loss) Error Event Counter */ 1656 #define DWT_EVC_RSE_OFFSET 0x06 1657 #define DWT_EVC_RSE_LEN 2 1658 #define DWT_EVC_RSE_MASK 0x0FFF 1659 1660 /* 1661 * The EVC_FCG field is a 12-bit counter of the frames received with 1662 * good CRC/FCS sequence. 1663 */ 1664 #define DWT_EVC_FCG_OFFSET 0x08 1665 #define DWT_EVC_FCG_LEN 2 1666 #define DWT_EVC_FCG_MASK 0x0FFF 1667 /* 1668 * The EVC_FCE field is a 12-bit counter of the frames received with 1669 * bad CRC/FCS sequence. 1670 */ 1671 #define DWT_EVC_FCE_OFFSET 0x0A 1672 #define DWT_EVC_FCE_LEN 2 1673 #define DWT_EVC_FCE_MASK 0x0FFF 1674 1675 /* 1676 * The EVC_FFR field is a 12-bit counter of the frames rejected 1677 * by the receive frame filtering function. 1678 */ 1679 #define DWT_EVC_FFR_OFFSET 0x0C 1680 #define DWT_EVC_FFR_LEN 2 1681 #define DWT_EVC_FFR_MASK 0x0FFF 1682 /* The EVC_OVR field is a 12-bit counter of receive overrun events */ 1683 #define DWT_EVC_OVR_OFFSET 0x0E 1684 #define DWT_EVC_OVR_LEN 2 1685 #define DWT_EVC_OVR_MASK 0x0FFF 1686 1687 /* The EVC_STO field is a 12-bit counter of SFD Timeout Error events */ 1688 #define DWT_EVC_STO_OFFSET 0x10 1689 #define DWT_EVC_OVR_LEN 2 1690 #define DWT_EVC_OVR_MASK 0x0FFF 1691 /* The EVC_PTO field is a 12-bit counter of Preamble detection Timeout events */ 1692 #define DWT_EVC_PTO_OFFSET 0x12 1693 #define DWT_EVC_PTO_LEN 2 1694 #define DWT_EVC_PTO_MASK 0x0FFF 1695 1696 /* 1697 * The EVC_FWTO field is a 12-bit counter of receive 1698 * frame wait timeout events 1699 */ 1700 #define DWT_EVC_FWTO_OFFSET 0x14 1701 #define DWT_EVC_FWTO_LEN 2 1702 #define DWT_EVC_FWTO_MASK 0x0FFF 1703 /* 1704 * The EVC_TXFS field is a 12-bit counter of transmit frames sent. 1705 * This is incremented every time a frame is sent 1706 */ 1707 #define DWT_EVC_TXFS_OFFSET 0x16 1708 #define DWT_EVC_TXFS_LEN 2 1709 #define DWT_EVC_TXFS_MASK 0x0FFF 1710 1711 /* The EVC_HPW field is a 12-bit counter of Half Period Warnings. */ 1712 #define DWT_EVC_HPW_OFFSET 0x18 1713 #define DWT_EVC_HPW_LEN 2 1714 #define DWT_EVC_HPW_MASK 0x0FFF 1715 /* The EVC_TPW field is a 12-bit counter of Transmitter Power-Up Warnings. */ 1716 #define DWT_EVC_TPW_OFFSET 0x1A 1717 #define DWT_EVC_TPW_LEN 2 1718 #define DWT_EVC_TPW_MASK 0x0FFF 1719 1720 /* 1721 * Offset from DIG_DIAG_ID in bytes, 1722 * Please take care not to write to this area as doing so 1723 * may cause the DW1000 to malfunction. 1724 */ 1725 #define DWT_EVC_RES1_OFFSET 0x1C 1726 1727 #define DWT_DIAG_TMC_OFFSET 0x24 1728 #define DWT_DIAG_TMC_LEN 2 1729 #define DWT_DIAG_TMC_MASK 0x0010 1730 /* 1731 * This test mode is provided to help support regulatory approvals 1732 * spectral testing. When the TX_PSTM bit is set it enables a 1733 * repeating transmission of the data from the TX_BUFFER 1734 */ 1735 #define DWT_DIAG_TMC_TX_PSTM 0x0010 1736 1737 #define DWT_REG_30_ID_RESERVED 0x30 1738 #define DWT_REG_31_ID_RESERVED 0x31 1739 #define DWT_REG_32_ID_RESERVED 0x32 1740 #define DWT_REG_33_ID_RESERVED 0x33 1741 #define DWT_REG_34_ID_RESERVED 0x34 1742 #define DWT_REG_35_ID_RESERVED 0x35 1743 1744 /* Power Management System Control Block */ 1745 #define DWT_PMSC_ID 0x36 1746 #define DWT_PMSC_LEN 48 1747 #define DWT_PMSC_CTRL0_OFFSET 0x00 1748 #define DWT_PMSC_CTRL0_LEN 4 1749 /* Access mask to register PMSC_CTRL0 */ 1750 #define DWT_PMSC_CTRL0_MASK 0xF18F847FUL 1751 /* 1752 * The system clock will run off the 19.2 MHz XTI clock until the PLL is 1753 * calibrated and locked, then it will switch over the 125 MHz PLL clock 1754 */ 1755 #define DWT_PMSC_CTRL0_SYSCLKS_AUTO 0x00000000UL 1756 /* Force system clock to be the 19.2 MHz XTI clock. */ 1757 #define DWT_PMSC_CTRL0_SYSCLKS_19M 0x00000001UL 1758 /* Force system clock to the 125 MHz PLL clock. */ 1759 #define DWT_PMSC_CTRL0_SYSCLKS_125M 0x00000002UL 1760 /* The RX clock will be disabled until it is required for an RX operation */ 1761 #define DWT_PMSC_CTRL0_RXCLKS_AUTO 0x00000000UL 1762 /* Force RX clock enable and sourced clock from the 19.2 MHz XTI clock */ 1763 #define DWT_PMSC_CTRL0_RXCLKS_19M 0x00000004UL 1764 /* Force RX clock enable and sourced from the 125 MHz PLL clock */ 1765 #define DWT_PMSC_CTRL0_RXCLKS_125M 0x00000008UL 1766 /* Force RX clock off. */ 1767 #define DWT_PMSC_CTRL0_RXCLKS_OFF 0x0000000CUL 1768 /* The TX clock will be disabled until it is required for a TX operation */ 1769 #define DWT_PMSC_CTRL0_TXCLKS_AUTO 0x00000000UL 1770 /* Force TX clock enable and sourced clock from the 19.2 MHz XTI clock */ 1771 #define DWT_PMSC_CTRL0_TXCLKS_19M 0x00000010UL 1772 /* Force TX clock enable and sourced from the 125 MHz PLL clock */ 1773 #define DWT_PMSC_CTRL0_TXCLKS_125M 0x00000020UL 1774 /* Force TX clock off */ 1775 #define DWT_PMSC_CTRL0_TXCLKS_OFF 0x00000030UL 1776 /* Force Accumulator Clock Enable */ 1777 #define DWT_PMSC_CTRL0_FACE 0x00000040UL 1778 /* GPIO clock enable */ 1779 #define DWT_PMSC_CTRL0_GPCE 0x00010000UL 1780 /* GPIO reset (NOT), active low */ 1781 #define DWT_PMSC_CTRL0_GPRN 0x00020000UL 1782 /* GPIO De-bounce Clock Enable */ 1783 #define DWT_PMSC_CTRL0_GPDCE 0x00040000UL 1784 /* Kilohertz Clock Enable */ 1785 #define DWT_PMSC_CTRL0_KHZCLEN 0x00800000UL 1786 /* Enable PLL2 on/off sequencing by SNIFF mode */ 1787 #define DWT_PMSC_CTRL0_PLL2_SEQ_EN 0x01000000UL 1788 #define DWT_PMSC_CTRL0_SOFTRESET_OFFSET 3 1789 /* Assuming only 4th byte of the register is read */ 1790 #define DWT_PMSC_CTRL0_RESET_ALL 0x00 1791 /* Assuming only 4th byte of the register is read */ 1792 #define DWT_PMSC_CTRL0_RESET_RX 0xE0 1793 /* Assuming only 4th byte of the register is read */ 1794 #define DWT_PMSC_CTRL0_RESET_CLEAR 0xF0 1795 #define DWT_PMSC_CTRL1_OFFSET 0x04 1796 #define DWT_PMSC_CTRL1_LEN 4 1797 /* Access mask to register PMSC_CTRL1 */ 1798 #define DWT_PMSC_CTRL1_MASK 0xFC02F802UL 1799 /* Automatic transition from receive mode into the INIT state */ 1800 #define DWT_PMSC_CTRL1_ARX2INIT 0x00000002UL 1801 /* 1802 * If this bit is set then the DW1000 will automatically transition 1803 * into SLEEP or DEEPSLEEP mode after transmission of a frame 1804 */ 1805 #define DWT_PMSC_CTRL1_ATXSLP 0x00000800UL 1806 /* 1807 * This bit is set then the DW1000 will automatically transition 1808 * into SLEEP mode after a receive attempt 1809 */ 1810 #define DWT_PMSC_CTRL1_ARXSLP 0x00001000UL 1811 /* Snooze Enable */ 1812 #define DWT_PMSC_CTRL1_SNOZE 0x00002000UL 1813 /* The SNOZR bit is set to allow the snooze timer to repeat twice */ 1814 #define DWT_PMSC_CTRL1_SNOZR 0x00004000UL 1815 /* This enables a special 1 GHz clock used for some external SYNC modes */ 1816 #define DWT_PMSC_CTRL1_PLLSYN 0x00008000UL 1817 /* This bit enables the running of the LDE algorithm */ 1818 #define DWT_PMSC_CTRL1_LDERUNE 0x00020000UL 1819 /* Kilohertz clock divisor */ 1820 #define DWT_PMSC_CTRL1_KHZCLKDIV_MASK 0xFC000000UL 1821 /* 1822 * Writing this to PMSC CONTROL 1 register (bits 10-3) disables 1823 * PMSC control of analog RF subsystems 1824 */ 1825 #define DWT_PMSC_CTRL1_PKTSEQ_DISABLE 0x00 1826 /* 1827 * Writing this to PMSC CONTROL 1 register (bits 10-3) enables 1828 * PMSC control of analog RF subsystems 1829 */ 1830 #define DWT_PMSC_CTRL1_PKTSEQ_ENABLE 0xE7 1831 #define DWT_PMSC_RES1_OFFSET 0x08 1832 /* PMSC Snooze Time Register */ 1833 #define DWT_PMSC_SNOZT_OFFSET 0x0C 1834 #define DWT_PMSC_SNOZT_LEN 1 1835 #define DWT_PMSC_RES2_OFFSET 0x10 1836 #define DWT_PMSC_RES3_OFFSET 0x24 1837 #define DWT_PMSC_TXFINESEQ_OFFSET 0x26 1838 /* Writing this disables fine grain sequencing in the transmitter */ 1839 #define DWT_PMSC_TXFINESEQ_DISABLE 0x0 1840 /* Writing this enables fine grain sequencing in the transmitter */ 1841 #define DWT_PMSC_TXFINESEQ_ENABLE 0x0B74 1842 #define DWT_PMSC_LEDC_OFFSET 0x28 1843 #define DWT_PMSC_LEDC_LEN 4 1844 /* 32-bit LED control register. */ 1845 #define DWT_PMSC_LEDC_MASK 0x000001FFUL 1846 /* 1847 * This field determines how long the LEDs remain lit after an event 1848 * that causes them to be set on. 1849 */ 1850 #define DWT_PMSC_LEDC_BLINK_TIM_MASK 0x000000FFUL 1851 /* Blink Enable. When this bit is set to 1 the LED blink feature is enabled. */ 1852 #define DWT_PMSC_LEDC_BLNKEN 0x00000100UL 1853 /* 1854 * Default blink time. Blink time is expressed in multiples of 14 ms. 1855 * The value defined here is ~225 ms. 1856 */ 1857 #define DWT_PMSC_LEDC_BLINK_TIME_DEF 0x10 1858 /* Command a blink of all LEDs */ 1859 #define DWT_PMSC_LEDC_BLINK_NOW_ALL 0x000F0000UL 1860 1861 #define DWT_REG_37_ID_RESERVED 0x37 1862 #define DWT_REG_38_ID_RESERVED 0x38 1863 #define DWT_REG_39_ID_RESERVED 0x39 1864 #define DWT_REG_3A_ID_RESERVED 0x3A 1865 #define DWT_REG_3B_ID_RESERVED 0x3B 1866 #define DWT_REG_3C_ID_RESERVED 0x3C 1867 #define DWT_REG_3D_ID_RESERVED 0x3D 1868 #define DWT_REG_3E_ID_RESERVED 0x3E 1869 #define DWT_REG_3F_ID_RESERVED 0x3F 1870 1871 1872 /* 1873 * Map the channel number to the index in the configuration arrays below. 1874 * Channel: na 1 2 3 4 5 na 7 1875 */ 1876 const uint8_t dwt_ch_to_cfg[] = {0, 0, 1, 2, 3, 4, 0, 5}; 1877 1878 /* Defaults from Table 38: Sub-Register 0x28:0C– RF_TXCTRL values */ 1879 const uint32_t dwt_txctrl_defs[] = { 1880 DWT_RF_TXCTRL_CH1, 1881 DWT_RF_TXCTRL_CH2, 1882 DWT_RF_TXCTRL_CH3, 1883 DWT_RF_TXCTRL_CH4, 1884 DWT_RF_TXCTRL_CH5, 1885 DWT_RF_TXCTRL_CH7, 1886 }; 1887 1888 /* Defaults from Table 43: Sub-Register 0x2B:07 – FS_PLLCFG values */ 1889 const uint32_t dwt_pllcfg_defs[] = { 1890 DWT_FS_PLLCFG_CH1, 1891 DWT_FS_PLLCFG_CH2, 1892 DWT_FS_PLLCFG_CH3, 1893 DWT_FS_PLLCFG_CH4, 1894 DWT_FS_PLLCFG_CH5, 1895 DWT_FS_PLLCFG_CH7 1896 }; 1897 1898 /* Defaults from Table 44: Sub-Register 0x2B:0B – FS_PLLTUNE values */ 1899 const uint8_t dwt_plltune_defs[] = { 1900 DWT_FS_PLLTUNE_CH1, 1901 DWT_FS_PLLTUNE_CH2, 1902 DWT_FS_PLLTUNE_CH3, 1903 DWT_FS_PLLTUNE_CH4, 1904 DWT_FS_PLLTUNE_CH5, 1905 DWT_FS_PLLTUNE_CH7 1906 }; 1907 1908 /* Defaults from Table 37: Sub-Register 0x28:0B– RF_RXCTRLH values */ 1909 const uint8_t dwt_rxctrlh_defs[] = { 1910 DWT_RF_RXCTRLH_NBW, 1911 DWT_RF_RXCTRLH_NBW, 1912 DWT_RF_RXCTRLH_NBW, 1913 DWT_RF_RXCTRLH_WBW, 1914 DWT_RF_RXCTRLH_NBW, 1915 DWT_RF_RXCTRLH_WBW 1916 }; 1917 1918 /* Defaults from Table 40: Sub-Register 0x2A:0B – TC_PGDELAY */ 1919 const uint8_t dwt_pgdelay_defs[] = { 1920 DWT_TC_PGDELAY_CH1, 1921 DWT_TC_PGDELAY_CH2, 1922 DWT_TC_PGDELAY_CH3, 1923 DWT_TC_PGDELAY_CH4, 1924 DWT_TC_PGDELAY_CH5, 1925 DWT_TC_PGDELAY_CH7 1926 }; 1927 1928 /* 1929 * Defaults from Table 19: Reference values for Register file: 1930 * 0x1E – Transmit Power Control for Smart Transmit Power Control 1931 * Transmit Power Control values for 16 MHz, with DIS_STXP = 0 1932 */ 1933 const uint32_t dwt_txpwr_stxp0_16[] = { 1934 0x15355575, 1935 0x15355575, 1936 0x0F2F4F6F, 1937 0x1F1F3F5F, 1938 0x0E082848, 1939 0x32527292 1940 }; 1941 1942 /* 1943 * Defaults from Table 19: Reference values for Register file: 1944 * 0x1E – Transmit Power Control for Smart Transmit Power Control 1945 * Transmit Power Control values for 64 MHz, with DIS_STXP = 0 1946 */ 1947 const uint32_t dwt_txpwr_stxp0_64[] = { 1948 0x07274767, 1949 0x07274767, 1950 0x2B4B6B8B, 1951 0x3A5A7A9A, 1952 0x25456585, 1953 0x5171B1D1 1954 }; 1955 1956 /* 1957 * Default from Table 20: Reference values Register file: 1958 * 0x1E – Transmit Power Control for Manual Transmit Power Control 1959 * Transmit Power Control values for 16 MHz, with DIS_STXP = 1 1960 */ 1961 const uint32_t dwt_txpwr_stxp1_16[] = { 1962 0x75757575, 1963 0x75757575, 1964 0x6F6F6F6F, 1965 0x5F5F5F5F, 1966 0x48484848, 1967 0x92929292 1968 }; 1969 1970 /* 1971 * Default from Table 20: Reference values Register file: 1972 * 0x1E – Transmit Power Control for Manual Transmit Power Control 1973 * Transmit Power Control values for 64 MHz, with DIS_STXP = 1 1974 */ 1975 const uint32_t dwt_txpwr_stxp1_64[] = { 1976 0x67676767, 1977 0x67676767, 1978 0x8B8B8B8B, 1979 0x9A9A9A9A, 1980 0x85858585, 1981 0xD1D1D1D1 1982 }; 1983 1984 enum dwt_pulse_repetition_frequency { 1985 DWT_PRF_16M = 0, 1986 DWT_PRF_64M, 1987 DWT_NUMOF_PRFS, 1988 }; 1989 1990 /* Defaults from Table 24: Sub-Register 0x23:04 – AGC_TUNE1 values */ 1991 const uint16_t dwt_agc_tune1_defs[] = { 1992 DWT_AGC_TUNE1_16M, 1993 DWT_AGC_TUNE1_64M 1994 }; 1995 1996 enum dwt_baud_rate { 1997 DWT_BR_110K = 0, 1998 DWT_BR_850K, 1999 DWT_BR_6M8, 2000 DWT_NUMOF_BRS, 2001 }; 2002 2003 /* Decawave non-standard SFD lengths */ 2004 const uint8_t dwt_ns_sfdlen[] = { 2005 DWT_DW_NS_SFD_LEN_110K, 2006 DWT_DW_NS_SFD_LEN_850K, 2007 DWT_DW_NS_SFD_LEN_6M8 2008 }; 2009 2010 /* Defaults from Table 30: Sub-Register 0x27:02 – DRX_TUNE0b values */ 2011 const uint16_t dwt_tune0b_defs[DWT_NUMOF_BRS][2] = { 2012 { 2013 DWT_DRX_TUNE0b_110K_STD, 2014 DWT_DRX_TUNE0b_110K_NSTD 2015 }, 2016 { 2017 DWT_DRX_TUNE0b_850K_STD, 2018 DWT_DRX_TUNE0b_850K_NSTD 2019 }, 2020 { 2021 DWT_DRX_TUNE0b_6M8_STD, 2022 DWT_DRX_TUNE0b_6M8_NSTD 2023 } 2024 }; 2025 2026 /* Defaults from Table 31: Sub-Register 0x27:04 – DRX_TUNE1a values */ 2027 const uint16_t dwt_tune1a_defs[] = { 2028 DWT_DRX_TUNE1a_PRF16, 2029 DWT_DRX_TUNE1a_PRF64 2030 }; 2031 2032 enum dwt_acquisition_chunk_size { 2033 DWT_PAC8 = 0, 2034 DWT_PAC16, 2035 DWT_PAC32, 2036 DWT_PAC64, 2037 DWT_NUMOF_PACS, 2038 }; 2039 2040 /* Defaults from Table 33: Sub-Register 0x27:08 – DRX_TUNE2 values */ 2041 const uint32_t dwt_tune2_defs[DWT_NUMOF_PRFS][DWT_NUMOF_PACS] = { 2042 { 2043 DWT_DRX_TUNE2_PRF16_PAC8, 2044 DWT_DRX_TUNE2_PRF16_PAC16, 2045 DWT_DRX_TUNE2_PRF16_PAC32, 2046 DWT_DRX_TUNE2_PRF16_PAC64 2047 }, 2048 { 2049 DWT_DRX_TUNE2_PRF64_PAC8, 2050 DWT_DRX_TUNE2_PRF64_PAC16, 2051 DWT_DRX_TUNE2_PRF64_PAC32, 2052 DWT_DRX_TUNE2_PRF64_PAC64 2053 } 2054 }; 2055 2056 /* 2057 * Defaults from Table 51: 2058 * Sub-Register 0x2E:2804 – LDE_REPC configurations for (850 kbps & 6.8 Mbps) 2059 * 2060 * For 110 kbps the values have to be divided by 8. 2061 */ 2062 const uint16_t dwt_lde_repc_defs[] = { 2063 0, 2064 DWT_LDE_REPC_PCODE_1, 2065 DWT_LDE_REPC_PCODE_2, 2066 DWT_LDE_REPC_PCODE_3, 2067 DWT_LDE_REPC_PCODE_4, 2068 DWT_LDE_REPC_PCODE_5, 2069 DWT_LDE_REPC_PCODE_6, 2070 DWT_LDE_REPC_PCODE_7, 2071 DWT_LDE_REPC_PCODE_8, 2072 DWT_LDE_REPC_PCODE_9, 2073 DWT_LDE_REPC_PCODE_10, 2074 DWT_LDE_REPC_PCODE_11, 2075 DWT_LDE_REPC_PCODE_12, 2076 DWT_LDE_REPC_PCODE_13, 2077 DWT_LDE_REPC_PCODE_14, 2078 DWT_LDE_REPC_PCODE_15, 2079 DWT_LDE_REPC_PCODE_16, 2080 DWT_LDE_REPC_PCODE_17, 2081 DWT_LDE_REPC_PCODE_18, 2082 DWT_LDE_REPC_PCODE_19, 2083 DWT_LDE_REPC_PCODE_20, 2084 DWT_LDE_REPC_PCODE_21, 2085 DWT_LDE_REPC_PCODE_22, 2086 DWT_LDE_REPC_PCODE_23, 2087 DWT_LDE_REPC_PCODE_24 2088 }; 2089 2090 enum dwt_plen_idx { 2091 DWT_PLEN_64 = 0, 2092 DWT_PLEN_128, 2093 DWT_PLEN_256, 2094 DWT_PLEN_512, 2095 DWT_PLEN_1024, 2096 DWT_PLEN_2048, 2097 DWT_PLEN_4096, 2098 DWT_NUM_OF_PLEN, 2099 }; 2100 2101 /* 2102 * Transmit Preamble Symbol Repetitions (TXPSR) and Preamble Extension (PE) 2103 * constants for TX_FCTRL - Transmit Frame Control register. 2104 * From Table 16: Preamble length selection 2105 * BIT(19) | BIT(18) | BIT(21) | BIT(20) 2106 */ 2107 const uint32_t dwt_plen_cfg[] = { 2108 (0 | BIT(18) | 0 | 0), 2109 (0 | BIT(18) | 0 | BIT(20)), 2110 (0 | BIT(18) | BIT(21) | 0), 2111 (0 | BIT(18) | BIT(21) | BIT(20)), 2112 (BIT(19) | 0 | 0 | 0), 2113 (BIT(19) | 0 | BIT(21) | 0), 2114 (BIT(19) | BIT(18) | 0 | 0), 2115 }; 2116 2117 /* 2118 * Noise Threshold Multiplier (default NTM is 13) and 2119 * Peak Multiplier (default PMULT is 3). 2120 */ 2121 #define DWT_DEFAULT_LDE_CFG1 ((3 << 5) | 13) 2122 2123 /* From Table 50: Sub-Register 0x2E:1806– LDE_CFG2 values */ 2124 #define DWT_DEFAULT_LDE_CFG2_PRF64 0x0607 2125 #define DWT_DEFAULT_LDE_CFG2_PRF16 0x1607 2126 2127 #define DWT_RX_SIG_PWR_A_CONST_PRF64 121.74 2128 #define DWT_RX_SIG_PWR_A_CONST_PRF16 113.77 2129 2130 #define DWT_DEVICE_ID 0xDECA0130 2131 #define DWT_SFDTOC_DEF 0x1041 2132 2133 #define DWT_OTP_LDOTUNE_ADDR 0x04 2134 #define DWT_OTP_PARTID_ADDR 0x06 2135 #define DWT_OTP_LOTID_ADDR 0x07 2136 #define DWT_OTP_VBAT_ADDR 0x08 2137 #define DWT_OTP_VTEMP_ADDR 0x09 2138 #define DWT_OTP_XTRIM_ADDR 0x1E 2139 2140 #endif /* ZEPHYR_INCLUDE_DW1000_REGS_H_ */ 2141
