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Searched refs:DT_INST_CHILD (Results 1 – 25 of 26) sorted by relevance

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/Zephyr-Core-3.7.0/drivers/display/
Ddisplay_stm32_ltdc.c518 .HSPolarity = (DT_PROP(DT_INST_CHILD(inst, display_timings), \
521 .VSPolarity = (DT_PROP(DT_INST_CHILD(inst, \
524 .DEPolarity = (DT_PROP(DT_INST_CHILD(inst, \
527 .PCPolarity = (DT_PROP(DT_INST_CHILD(inst, \
530 .HorizontalSync = DT_PROP(DT_INST_CHILD(inst, \
532 .VerticalSync = DT_PROP(DT_INST_CHILD(inst, \
534 .AccumulatedHBP = DT_PROP(DT_INST_CHILD(inst, \
536 DT_PROP(DT_INST_CHILD(inst, \
538 .AccumulatedVBP = DT_PROP(DT_INST_CHILD(inst, \
540 DT_PROP(DT_INST_CHILD(inst, \
[all …]
Ddisplay_mcux_dcnano_lcdif.c308 .hsw = DT_PROP(DT_INST_CHILD(n, display_timings), \
310 .hfp = DT_PROP(DT_INST_CHILD(n, display_timings), \
312 .hbp = DT_PROP(DT_INST_CHILD(n, display_timings), \
314 .vsw = DT_PROP(DT_INST_CHILD(n, display_timings), \
316 .vfp = DT_PROP(DT_INST_CHILD(n, display_timings), \
318 .vbp = DT_PROP(DT_INST_CHILD(n, display_timings), \
320 .polarityFlags = (DT_PROP(DT_INST_CHILD(n, \
324 (DT_PROP(DT_INST_CHILD(n, \
328 (DT_PROP(DT_INST_CHILD(n, \
332 (DT_PROP(DT_INST_CHILD(n, \
Ddisplay_renesas_lcdc.c36 !!(32000000U % DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency))
141 LCDC_SMARTBOND_CLK_DIV(DT_PROP(DT_INST_CHILD(0, display_timings), clock_frequency)); in display_smartbond_configure()
638 DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_len), \
640 DT_PROP(DT_INST_CHILD(inst, display_timings), hsync_len), \
642 DT_PROP(DT_INST_CHILD(inst, display_timings), hfront_porch), \
644 DT_PROP(DT_INST_CHILD(inst, display_timings), vfront_porch), \
646 DT_PROP(DT_INST_CHILD(inst, display_timings), hback_porch), \
648 DT_PROP(DT_INST_CHILD(inst, display_timings), vback_porch), \
655 DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
657 DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_active) ? 0 : 1, \
[all …]
Ddisplay_mcux_elcdif.c371 .hsw = DT_PROP(DT_INST_CHILD(id, display_timings), hsync_len), \
372 .hfp = DT_PROP(DT_INST_CHILD(id, display_timings), hfront_porch), \
373 .hbp = DT_PROP(DT_INST_CHILD(id, display_timings), hback_porch), \
374 .vsw = DT_PROP(DT_INST_CHILD(id, display_timings), vsync_len), \
375 .vfp = DT_PROP(DT_INST_CHILD(id, display_timings), vfront_porch), \
376 .vbp = DT_PROP(DT_INST_CHILD(id, display_timings), vback_porch), \
378 (DT_PROP(DT_INST_CHILD(id, display_timings), hsync_active) \
381 (DT_PROP(DT_INST_CHILD(id, display_timings), vsync_active) \
384 (DT_PROP(DT_INST_CHILD(id, display_timings), de_active) \
387 (DT_PROP(DT_INST_CHILD(id, display_timings), \
/Zephyr-Core-3.7.0/drivers/regulator/
Dregulator_npm1100.c122 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, buck)), \
123 (REGULATOR_NPM1100_DEFINE_BUCK(DT_INST_CHILD(inst, buck), \
Dregulator_adp5360.c300 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
301 (REGULATOR_ADP5360_DEFINE(DT_INST_CHILD(inst, child), child##inst, child)), \
Dregulator_max20335.c358 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
359 (REGULATOR_MAX20335_DEFINE(DT_INST_CHILD(inst, child), \
Dregulator_axp192.c382 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
383 (REGULATOR_AXP192_DEFINE(DT_INST_CHILD(inst, child), child##inst, child)), ())
Dregulator_da1469x.c475 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
477 DT_INST_CHILD(inst, child), child, source)), \
Dregulator_npm6001.c597 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
598 (REGULATOR_NPM6001_DEFINE(DT_INST_CHILD(inst, child), child##inst, source)), \
Dregulator_pca9420.c530 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
531 (REGULATOR_PCA9420_DEFINE(DT_INST_CHILD(inst, child), \
Dregulator_npm1300.c662 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
663 (REGULATOR_NPM1300_DEFINE(DT_INST_CHILD(inst, child), child##inst, source)), \
/Zephyr-Core-3.7.0/drivers/misc/nxp_s32_emios/
Dnxp_s32_emios.c78 DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
81 DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
/Zephyr-Core-3.7.0/drivers/gpio/
Dgpio_xlnx_axi.c384 UTIL_AND(DT_NODE_HAS_COMPAT(DT_INST_CHILD(n, gpio2), xlnx_xps_gpio_1_00_a_gpio2), \
385 DT_NODE_HAS_STATUS(DT_INST_CHILD(n, gpio2), okay))
410 DEVICE_DT_DEFINE(DT_INST_CHILD(n, gpio2), &gpio_xlnx_axi_init, NULL, \
426 (.other_channel_device = DEVICE_DT_GET(DT_INST_CHILD(n, gpio2))))}; \
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_mcux_scg.c22 #define MCUX_SCG_CLOCK_NODE(name) DT_INST_CHILD(0, name)
/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_eirq_nxp_s32.c226 COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(n, irq_##idx)), \
227 (DT_PROP_OR(DT_INST_CHILD(n, irq_##idx), max_filter_counter, \
Dintc_wkpu_nxp_s32.c195 COND_CODE_1(DT_PROP(DT_INST_CHILD(n, irq_##idx), filter_enable), (BIT(idx)), (0U))
/Zephyr-Core-3.7.0/drivers/flash/
Dflash_simulator.c31 #define SOC_NV_FLASH_NODE DT_INST_CHILD(0, flash_0)
33 #define SOC_NV_FLASH_NODE DT_INST_CHILD(0, flash_sim_0)
/Zephyr-Core-3.7.0/drivers/ethernet/
Deth_e1000.c25 #define PTP_INST_NODEID(n) DT_INST_CHILD(n, ptp)
Deth_adin2111.c1521 DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(adin_n, mdio), ethernet_phy_##phy_addr))
Deth_stm32_hal.c62 DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(n, mdio), ethernet_phy_0))
/Zephyr-Core-3.7.0/drivers/counter/
Dcounter_mcux_lpc_rtc.c238 .rtc_dev = DEVICE_DT_GET_OR_NULL(DT_INST_CHILD(id, rtc_highres)), \
/Zephyr-Core-3.7.0/include/zephyr/
Ddevicetree.h3633 #define DT_INST_CHILD(inst, child) \ macro
/Zephyr-Core-3.7.0/tests/lib/devicetree/api/src/
Dmain.c2142 zassert_equal(DT_PROP(DT_INST_CHILD(0, child_a), val), 0, ""); in ZTEST()
2143 zassert_equal(DT_PROP(DT_INST_CHILD(0, child_b), val), 1, ""); in ZTEST()
2144 zassert_equal(DT_PROP(DT_INST_CHILD(0, child_c), val), 2, ""); in ZTEST()
/Zephyr-Core-3.7.0/drivers/ethernet/nxp_enet/
Deth_mcux.c1340 #define PTP_INST_NODEID(n) DT_INST_CHILD(n, ptp)

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