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Searched refs:DT_INST (Results 1 – 25 of 201) sorted by relevance

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/Zephyr-Core-3.7.0/boards/snps/em_starterkit/
Darc_mpu_regions.c16 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
19 DT_REG_ADDR(DT_INST(0, arc_iccm)),
20 DT_REG_SIZE(DT_INST(0, arc_iccm)),
23 #if DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0
26 DT_REG_ADDR(DT_INST(0, arc_dccm)),
27 DT_REG_SIZE(DT_INST(0, arc_dccm)),
31 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
34 DT_REG_ADDR(DT_INST(0, arc_xccm)),
35 DT_REG_SIZE(DT_INST(0, arc_xccm)),
38 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
[all …]
/Zephyr-Core-3.7.0/drivers/display/
Ddisplay_ili9341.h85 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), gamset) == ILI9341_GAMSET_LEN, \
87 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ifmode) == ILI9341_IFMODE_LEN, \
89 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), frmctr1) == ILI9341_FRMCTR1_LEN, \
91 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), disctrl) == ILI9341_DISCTRL_LEN, \
93 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl1) == ILI9341_PWCTRL1_LEN, \
95 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl2) == ILI9341_PWCTRL2_LEN, \
97 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl1) == ILI9341_VMCTRL1_LEN, \
99 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl2) == ILI9341_VMCTRL2_LEN, \
101 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pgamctrl) == ILI9341_PGAMCTRL_LEN, \
103 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ngamctrl) == ILI9341_NGAMCTRL_LEN, \
[all …]
Ddisplay_ili9342c.h71 .gamset = DT_PROP(DT_INST(n, ilitek_ili9342c), gamset), \
72 .ifmode = DT_PROP(DT_INST(n, ilitek_ili9342c), ifmode), \
73 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9342c), frmctr1), \
74 .invtr = DT_PROP(DT_INST(n, ilitek_ili9342c), invtr), \
75 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), disctrl), \
76 .etmod = DT_PROP(DT_INST(n, ilitek_ili9342c), etmod), \
77 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl1), \
78 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl2), \
79 .pwctrl3 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl3), \
80 .vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), vmctrl1), \
[all …]
Ddisplay_ili9340.h54 .gamset = DT_PROP(DT_INST(n, ilitek_ili9340), gamset), \
55 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9340), frmctr1), \
56 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9340), disctrl), \
57 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9340), pwctrl1), \
58 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9340), pwctrl2), \
59 .vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9340), vmctrl1), \
60 .vmctrl2 = DT_PROP(DT_INST(n, ilitek_ili9340), vmctrl2), \
61 .pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9340), pgamctrl), \
62 .ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9340), ngamctrl), \
Ddisplay_ili9488.h48 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9488), frmctr1), \
49 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9488), disctrl), \
50 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl1), \
51 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl2), \
52 .vmctrl = DT_PROP(DT_INST(n, ilitek_ili9488), vmctrl), \
53 .pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), pgamctrl), \
54 .ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), ngamctrl), \
/Zephyr-Core-3.7.0/boards/snps/emsdp/
Darc_mpu_regions.c14 DT_REG_ADDR(DT_INST(0, arc_iccm)),
15 DT_REG_SIZE(DT_INST(0, arc_iccm)),
19 DT_REG_ADDR(DT_INST(0, arc_dccm)),
20 DT_REG_SIZE(DT_INST(0, arc_dccm)),
23 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
25 DT_REG_ADDR(DT_INST(0, arc_xccm)),
26 DT_REG_SIZE(DT_INST(0, arc_xccm)),
30 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
32 DT_REG_ADDR(DT_INST(0, arc_yccm)),
33 DT_REG_SIZE(DT_INST(0, arc_yccm)),
[all …]
/Zephyr-Core-3.7.0/boards/snps/iotdk/
Darc_mpu_regions.c14 DT_REG_ADDR(DT_INST(0, arc_iccm)),
15 DT_REG_SIZE(DT_INST(0, arc_iccm)),
19 DT_REG_ADDR(DT_INST(0, arc_dccm)),
20 DT_REG_SIZE(DT_INST(0, arc_dccm)),
23 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
25 DT_REG_ADDR(DT_INST(0, arc_xccm)),
26 DT_REG_SIZE(DT_INST(0, arc_xccm)),
30 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
32 DT_REG_ADDR(DT_INST(0, arc_yccm)),
33 DT_REG_SIZE(DT_INST(0, arc_yccm)),
/Zephyr-Core-3.7.0/boards/snps/nsim/arc_classic/
Darc_mpu_regions.c27 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
30 DT_REG_ADDR(DT_INST(0, arc_iccm)),
31 DT_REG_SIZE(DT_INST(0, arc_iccm)),
34 #if DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0
37 DT_REG_ADDR(DT_INST(0, arc_dccm)),
38 DT_REG_SIZE(DT_INST(0, arc_dccm)),
41 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
44 DT_REG_ADDR(DT_INST(0, arc_xccm)),
45 DT_REG_SIZE(DT_INST(0, arc_xccm)),
48 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
[all …]
/Zephyr-Core-3.7.0/include/zephyr/arch/arc/v2/
Dxy_mem.ld7 #if DT_NODE_HAS_PROP(DT_INST(0, arc_xccm), reg) && \
8 (DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0)
9 #define XCCM_START DT_REG_ADDR(DT_INST(0, arc_xccm))
10 #define XCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_xccm))
13 #if DT_NODE_HAS_PROP(DT_INST(0, arc_yccm), reg) && \
14 (DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0)
15 #define YCCM_START DT_REG_ADDR(DT_INST(0, arc_yccm))
16 #define YCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_yccm))
/Zephyr-Core-3.7.0/soc/snps/emsk/
Dsoc_config.c20 #if DT_NODE_HAS_STATUS(DT_INST(0, ns16550), okay) in uart_ns16550_init()
21 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x4); in uart_ns16550_init()
22 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x10); in uart_ns16550_init()
24 #if DT_NODE_HAS_STATUS(DT_INST(1, ns16550), okay) in uart_ns16550_init()
25 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x4); in uart_ns16550_init()
26 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x10); in uart_ns16550_init()
Dlinker.ld26 #if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
27 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
28 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
29 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
36 #if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
37 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
38 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
39 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_mcux_sim.c70 #if DT_NODE_HAS_STATUS(DT_INST(0, nxp_kinetis_ke1xf_sim), okay)
71 #define NXP_KINETIS_SIM_NODE DT_INST(0, nxp_kinetis_ke1xf_sim)
72 #if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_ke1xf_sim), clkout_source)
74 DT_PROP(DT_INST(0, nxp_kinetis_ke1xf_sim), clkout_source)
76 #if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_ke1xf_sim), clkout_divider)
78 DT_PROP(DT_INST(0, nxp_kinetis_ke1xf_sim), clkout_divider)
81 #define NXP_KINETIS_SIM_NODE DT_INST(0, nxp_kinetis_sim)
82 #if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_sim), clkout_source)
84 DT_PROP(DT_INST(0, nxp_kinetis_sim), clkout_source)
86 #if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_sim), clkout_divider)
[all …]
/Zephyr-Core-3.7.0/samples/application_development/code_relocation_nocopy/
Dlinker_arm_nocopy.ld24 #define EXTFLASH_NODE DT_INST(0, nordic_qspi_nor)
29 #elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_ospi_nor))
32 #define EXTFLASH_NODE DT_INST(0, st_stm32_ospi_nor)
33 #define EXTFLASH_ADDR DT_REG_ADDR(DT_INST(0, st_stm32_ospi_nor))
34 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_ospi_nor), 1)
36 #elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_qspi_nor))
39 #define EXTFLASH_NODE DT_INST(0, st_stm32_qspi_nor)
40 #define EXTFLASH_ADDR DT_REG_ADDR(DT_INST(0, st_stm32_qspi_nor))
41 #define EXTFLASH_SIZE DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_qspi_nor), 1)
43 #elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_xspi_nor))
[all …]
/Zephyr-Core-3.7.0/tests/drivers/gpio/gpio_basic_api/src/
Dtest_gpio.h15 #if DT_NODE_HAS_STATUS(DT_INST(0, test_gpio_basic_api), okay)
24 #define DEV_OUT DT_GPIO_CTLR(DT_INST(0, test_gpio_basic_api), out_gpios)
25 #define DEV_IN DT_GPIO_CTLR(DT_INST(0, test_gpio_basic_api), in_gpios)
27 #define PIN_OUT DT_GPIO_PIN(DT_INST(0, test_gpio_basic_api), out_gpios)
28 #define PIN_OUT_FLAGS DT_GPIO_FLAGS(DT_INST(0, test_gpio_basic_api), out_gpios)
29 #define PIN_IN DT_GPIO_PIN(DT_INST(0, test_gpio_basic_api), in_gpios)
30 #define PIN_IN_FLAGS DT_GPIO_FLAGS(DT_INST(0, test_gpio_basic_api), in_gpios)
/Zephyr-Core-3.7.0/soc/snps/emsdp/
Dlinker.ld25 #if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
26 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
27 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
28 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
35 #if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
36 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
37 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
38 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-3.7.0/soc/snps/arc_iot/
Dlinker.ld30 #if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
31 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
32 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
33 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
39 #if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
40 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
41 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
42 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-3.7.0/include/zephyr/arch/arm/cortex_m/
Dnvic.h17 #define NVIC_NODEID DT_INST(0, arm_v8_1m_nvic)
19 #define NVIC_NODEID DT_INST(0, arm_v8m_nvic)
21 #define NVIC_NODEID DT_INST(0, arm_v7m_nvic)
23 #define NVIC_NODEID DT_INST(0, arm_v6m_nvic)
/Zephyr-Core-3.7.0/soc/arm/fvp_aemv8a/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/arm/qemu_cortex_a53/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
15 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
20 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/arm/qemu_virt_arm64/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
15 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
20 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/brcm/bcm2711/
Dmmu_regions.c12 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
13 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
17 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
18 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/brcm/bcm2712/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/xen/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/rockchip/rk3399/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
/Zephyr-Core-3.7.0/soc/nxp/layerscape/ls1046a/
Dmmu_regions.c13 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
14 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
18 DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
19 DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),

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