1 /* Copyright (c) 2022 Intel Corporation
2 * SPDX-License-Identifier: Apache-2.0
3 */
4
5 #ifndef INTEL_COMM_WIDGET_H
6 #define INTEL_COMM_WIDGET_H
7
8 #include <zephyr/cache.h>
9 #include <zephyr/kernel.h>
10
11 #define CW_DT_NODE DT_NODELABEL(ace_comm_widget)
12 #define CW_BASE DT_REG_ADDR(CW_DT_NODE)
13
14 /*
15 * @brief DSP Communication Widget for Intel ADSP
16 *
17 * These registers control the DSP Communication Widget for generic sideband message transmit /
18 * receive.
19 */
20
21 /*
22 * Downstream Attributes
23 * Attribute register for downstream message.
24 */
25 #define DSATTR 0x00
26
27 /*
28 * Destination Port ID
29 * type: RO/V, rst: 00h
30 *
31 * Destination Port ID received in message.
32 */
33 #define DSATTR_DSTPID GENMASK(7, 0)
34
35 /*
36 * Source Port ID
37 * type: RO/V, rst: 00h
38 *
39 * Source Port ID received in message.
40 */
41 #define DSATTR_SRCPID GENMASK(15, 8)
42
43 /*
44 * Opcode
45 * type: RO/V, rst: 00h
46 *
47 * Opcode received in message.
48 */
49 #define DSATTR_OPC GENMASK(23, 16)
50
51 /*
52 * Byte Enable
53 * type: RO/V, rst: 0h
54 *
55 * Byte enables received in message.
56 */
57 #define DSATTR_BE GENMASK(27, 24)
58
59 /*
60 * Reserved
61 * type: RO, rst: 0h
62 */
63 #define DSATTR_RSVD31 GENMASK(31, 28)
64
65
66 /*
67 * Downstream Lower Address
68 * Address register (lower 32 bits) for downstream message.
69 *
70 * type: RO/V, rst: 0000 0000h
71 *
72 * LSB 32 address bits received in message. Bits 32:16 of the LSB address only
73 * valid when DSUADDR.ADDRLEN bit is set to 1.
74 */
75 #define DSLADDR 0x04
76
77
78 /*
79 * Downstream Upper Address
80 * Address register (upper 32 bits) for downstream message.
81 */
82 #define DSUADDR 0x08
83
84 /*
85 * Upper Address
86 * type: RO/V, rst: 0000h
87 *
88 * MSB 16 address bits received in message. Valid only when ADDRLEN bit is set to 1.
89 */
90 #define DSUADDR_UADDR GENMASK(15, 0)
91
92 /*
93 * Reserved
94 * type: RO, rst: 0000h
95 */
96 #define DSUADDR_RSVD30 GENMASK(30, 16)
97
98 /*
99 * Address Length
100 * type: RO/V, rst: 0b
101 *
102 * Address length indication received in message.
103 * 0: 16-bit address
104 * 1: 48-bit address
105 */
106 #define DSUADDR_ADDRLEN BIT(31)
107
108
109 /*
110 * Downstream SAI
111 * Extended header (SAI / RS) register for downstream message.
112 */
113 #define DSSAI 0x0C
114
115 /*
116 * SAI
117 * type: RO/V, rst: 0000h
118 *
119 * SAI received in message. Valid if EHP bit set to 1.
120 */
121 #define DSSAI_SAI GENMASK(15, 0)
122
123 /*
124 * Root Space
125 * type: RO/V, rst: 0h
126 *
127 * Root space received in message. Valid if EHP bit set to 1.
128 */
129 #define DSSAI_RS GENMASK(19, 16)
130
131 /*
132 * Reserved
133 * type: RO, rst: 000h
134 */
135 #define DSSAI_RSVD30 GENMASK(30, 20)
136
137 /*
138 * Extended Header Present
139 * type: RO/V, rst: 0b
140 *
141 * Extended header present indication received in message. When set to 1 indicates
142 * extended header is present, and RS / SAI fields are valid.
143 */
144 #define DSSAI_EHP BIT(31)
145
146
147 /*
148 * Downstream Data
149 * Receive data register for downstream message.
150 *
151 * type: RO/V, rst: 0000 0000h
152 *
153 * Data received in message.
154 */
155 #define DSDATA 0x10
156
157
158 /*
159 * Downstream Control & Status
160 * Control & status register for downstream message.
161 */
162 #define DSCTLSTS 0x14
163
164 /*
165 * Transaction Type
166 * type: RO/V, rst: 00b
167 *
168 * Indicates type of transaction received as follows:
169 * 01: Posted message
170 * 10: Non-posted message
171 * 11: Completion message.
172 */
173 #define DSCTLSTS_TRANTYP GENMASK(1, 0)
174
175 /*
176 * Reserved
177 * type: RO, rst: 000 0000h
178 */
179 #define DSCTLSTS_RSVD29 GENMASK(29, 2)
180
181 /*
182 * Interrupt GENMASK
183 * type: RW, rst: 0b, rst domain: gHSTRST
184 *
185 * Interrupt GENMASK register for message received interrupt. When set to 1 interrupt
186 * is not generated to DSP Core. GENMASK does not affect interrupt status bit.
187 */
188 #define DSCTLSTS_IM BIT(30)
189
190 /*
191 * Message Received
192 * type: RO/V, rst: 0b
193 *
194 * Message received interrupt status register. Set by HW when message is received,
195 * and cleared by HW when FW writes to upstream completion control register
196 * indicating completion is available.
197 */
198 #define DSCTLSTS_MSGRCV BIT(31)
199
200
201 /*
202 * Downstream Source Port ID
203 * Source port ID register for ACE IP.
204 */
205 #define ACESRCPID 0x18
206
207 /*
208 * Source Port ID
209 * type: RO/V, rst: ACE_SRCID
210 *
211 * Source Port ID of ACE IP. Default value is hardcoded to parameter ACE_SRCID.
212 */
213 #define ACESRCPID_SRCPID GENMASK(7, 0)
214
215 /*
216 * Reserved
217 * type: RO, rst: 00 0000h
218 */
219 #define ACESRCPID_RSVD31 GENMASK(31, 8)
220
221
222 /*
223 * Downstream Completion Data
224 *
225 * type: RO/V, rst: 0000 0000h
226 *
227 * Completion data received for upstream non-posted read.
228 */
229 #define DSCPDATA 0x20
230
231
232 /*
233 * Downstream Completion SAI
234 *
235 * type: RO/V, rst: 0000 0000h
236 *
237 * Completion SAI received for upstream non-posted message.
238 */
239 #define DSCPSAI 0x24
240
241
242 /*
243 * Downstream Completion Control & Status
244 */
245 #define DSCPCTLSTS 0x28
246
247 /*
248 * Completion Status
249 * type: RO/V, rst: 0b
250 *
251 * Completion status received for upstream non-posted message
252 * 000: Successful Completion (SC)
253 * 001: Unsupported Request (UR).
254 */
255 #define DSCPCTLSTS_CPSTS GENMASK(2, 0)
256
257 /*
258 * Reserved
259 * type: RO, rst: 0b
260 */
261 #define DSCPCTLSTS_RSVD7 GENMASK(7, 3)
262
263 /*
264 * Completion Extended Header Present
265 * type: RO/V, rst: 0b
266 *
267 * Completion EH present indication received for upstream non-posted message.
268 */
269 #define DSCPCTLSTS_CPEHP BIT(8)
270
271 /*
272 * Reserved
273 * type: RO, rst: 00 0000h
274 */
275 #define DSCPCTLSTS_RSVD29 GENMASK(29, 9)
276
277 /*
278 * Interrupt GENMASK
279 * type: RW, rst: 0b, rst domain: gHSTRST
280 *
281 * Interrupt GENMASK register for completion received interrupt. When set to 1
282 * interrupt is not generated to DSP Core. GENMASK does not affect interrupt status
283 * bit.
284 */
285 #define DSCPCTLSTS_IM BIT(30)
286
287 /*
288 * Completion Received
289 * type: RW/1C, rst: 0b, rst domain: gHSTRST
290 *
291 * Completion received status register. Set by HW when completion is received, and
292 * cleared by FW when writing 1 to it.
293 */
294 #define DSCPCTLSTS_CPRCV BIT(31)
295
296
297 /*
298 * Upstream Status
299 * Status register for upstream message.
300 */
301 #define USSTS 0x40
302
303 /*
304 * State Machine Status
305 * type: RO/V, rst: 0b
306 *
307 * 0: The Endpoint Status Machine is idle
308 * 1: The Endpoint State Machine is busy
309 * This is OR of posted SM and non-posted SM busy signals.
310 */
311 #define USSTS_SMSTS BIT(0)
312
313 /*
314 * Message Sent
315 * type: RW/1C, rst: 0b, rst domain: gHSTRST
316 *
317 * Upstream message sent interrupt status. Set by HW when upstream message has been
318 * sent out, and cleared by FW when writing 1 to it.
319 */
320 #define USSTS_MSGSENT BIT(1)
321
322 /*
323 * Reserved
324 * type: RO, rst: 0000 0000h
325 */
326 #define USSTS_RSVD31 GENMASK(31, 2)
327
328
329 /*
330 * Upstream Command
331 * Command register for upstream message.
332 */
333 #define USCMD 0x44
334
335 /*
336 * Send Sideband Transaction
337 * type: WO, rst: 0b
338 *
339 * DSP FW writes a 1 to this bit to cause an IOSF SB Transaction. The type of
340 * transaction is determined by Bit 1 in this register. This bit will always be
341 * read as 0 but FW can write it to 1 to start the upstream transaction. In that way
342 * it won't be readable as 1 after writing to. The write to this bit is ignored by
343 * hardware if opcode is 0x20 - 0x2F.
344 */
345 #define USCMD_SSBTRAN BIT(0)
346
347 /*
348 * Transaction Type
349 * type: RW, rst: 0b, rst domain: gHSTRST
350 *
351 * 0: Transaction will be a Write
352 * 1: Transaction will be a Read
353 * For posted message this register bit value will be ignored and hardcoded to 0 in
354 * the actual message as reads cannot be posted.
355 */
356 #define USCMD_TRANTYP BIT(1)
357
358 /*
359 * Message Type
360 * type: RW, rst: 0b, rst domain: gHSTRST
361 *
362 * 0: Transaction will be non-posted
363 * 1: Transaction will be posted
364 */
365 #define USCMD_MSGTYP BIT(2)
366
367 /*
368 * Interrupt Enable
369 * type: RW, rst: 0b, rst domain: gHSTRST
370 *
371 * Interrupt enable register for message sent interrupt. When cleared to 0 interrupt
372 * is not generated to DSP Core. Enable does not affect interrupt status bit.
373 */
374 #define USCMD_IE BIT(3)
375
376 /*
377 * Reserved
378 * type: RO, rst: 000 0000h
379 */
380 #define USCMD_RSVD31 GENMASK(31, 4)
381
382
383 /*
384 * Upstream Lower Address
385 * Address register (lower 32 bits) for upstream message.
386 *
387 * type: RW, rst: 0000 0000h, rst domain: gHSTRST
388 *
389 * LSB 32 address bits for message to be sent. Bits 32:16 of the LSB address only
390 * valid when USUADDR.ADDRLEN bit is set to 1.
391 */
392 #define USLADDR 0x48
393
394
395 /*
396 * Upstream Upper Address
397 * Address register (upper 32 bits) for upstream message.
398 */
399 #define USUADDR 0x4C
400
401 /*
402 * Upper Address
403 * type: RW, rst: 0000h, rst domain: gHSTRST
404 *
405 * MSB 16 address bits for message to be sent. Valid only when ADDRLEN bit is set
406 * to 1.
407 */
408 #define USUADDR_UADDR GENMASK(15, 0)
409
410 /*
411 * Reserved
412 * type: RO, rst: 0000h
413 */
414 #define USUADDR_RSVD30 GENMASK(30, 16)
415
416 /*
417 * Address Length
418 * type: RW, rst: 0b, rst domain: gHSTRST
419 *
420 * Address length indication for message to be sent.
421 * 0: 16-bit address
422 * 1: 48-bit address
423 * For simple message / message with data, this field will carry the MISC[3] of the
424 * IOSF 1.2 message format.
425 */
426 #define USUADDR_ADDRLEN BIT(31)
427
428
429 /*
430 * Upstream Data
431 * Transmit data register for upstream message.
432 *
433 * type: RW, rst: 0000 0000h, rst domain: gHSTRST
434 *
435 * Data for message to be sent.
436 */
437 #define USDATA 0x50
438
439
440 /*
441 * Upstream Attributes
442 * Attribute register for upstream message.
443 */
444 #define USATTR 0x54
445
446 /*
447 * Destination Port ID
448 * type: RW, rst: 00h, rst domain: gHSTRST
449 *
450 * Destination ID for message to be sent.
451 */
452 #define USATTR_DSTPID GENMASK(7, 0)
453
454 /*
455 * Opcode
456 * type: RW, rst: 00h, rst domain: gHSTRST
457 *
458 * Opcode for message to be sent.
459 */
460 #define USATTR_OPC GENMASK(15, 8)
461
462 /*
463 * Byte Enable
464 * type: RW, rst: 0h, rst domain: gHSTRST
465 *
466 * Byte enables for message to be sent.
467 */
468 #define USATTR_BE GENMASK(19, 16)
469
470 /*
471 * Base Address Register
472 * type: RW, rst: 0h, rst domain: gHSTRST
473 *
474 * BAR for register access to be sent. For simple message / message with data, this
475 * field will carry the MISC[2:0] of the IOSF 1.2 message format. Note: MSB of this
476 * register field is not used given the IOSF Sideband message BAR field is ONLY 3
477 * bits wide; and MISC[3] of the IOSF 1.2 message format is supplied by
478 * USUADDR.ADDRLEN.
479 */
480 #define USATTR_BAR GENMASK(23, 20)
481
482 /*
483 * Function ID
484 * type: RW, rst: 00h, rst domain: gHSTRST
485 *
486 * Function ID for register access to be sent.
487 */
488 #define USATTR_FID GENMASK(31, 24)
489
490
491 /*
492 * Upstream SAI
493 * Extended header (SAI / RS) register for upstream message.
494 */
495 #define USSAI 0x58
496
497 /*
498 * SAI
499 * type: RO, rst: DSPISAI_2SB
500 *
501 * SAI for message to be sent, if EHP bit set to 1. Reset value is hardcoded to
502 * parameter DSPISAI_2SB.
503 */
504 #define USSAI_SAI GENMASK(7, 0)
505
506 /*
507 * Reserved
508 * type: RO, rst: 00h
509 */
510 #define USSAI_RSVD15 GENMASK(15, 8)
511
512 /*
513 * Root Space
514 * type: RW, rst: 0h, rst domain: gHSTRST
515 *
516 * Root space for message to be sent, if EHP bit set to 1.
517 */
518 #define USSAI_RS GENMASK(19, 16)
519
520 /*
521 * Reserved
522 * type: RO, rst: 000h
523 */
524 #define USSAI_RSVD30 GENMASK(30, 20)
525
526 /*
527 * Extended Header Present
528 * type: RO, rst: 1b
529 *
530 * Extended header present indication for message to be sent. When set to 1
531 * indicates extended header is present. Currently tied to 1 in RTL as ACE IP
532 * supports only EH=1 transactions.
533 */
534 #define USSAI_EHP BIT(31)
535
536
537 /*
538 * Upstream Completion Data
539 *
540 * type: RW, rst: 0000 0000h, rst domain: gHSTRST
541 *
542 * Completion data to be sent for downstream non-posted read.
543 */
544 #define USCPDATA 0x5C
545
546
547 /*
548 * Upstream Completion Control & Status
549 */
550 #define USCPCTLSTS 0x60
551
552 /*
553 * Completion Status
554 * type: RW, rst: 0h, rst domain: gHSTRST
555 *
556 * Completion status to be sent for downstream non-posted message.
557 * 000: Successful Completion (SC)
558 * 001: Unsupported Request (UR).
559 */
560 #define USCPCTLSTS_CPSTS GENMASK(2, 0)
561
562 /*
563 * Reserved
564 * type: RO, rst: 000 0000h
565 */
566 #define USCPCTLSTS_RSVD30 GENMASK(30, 3)
567
568 /*
569 * Sideband Completion
570 * type: RW/1S, rst: 0h, rst domain: gHSTRST
571 *
572 * Completion for downstream request handling. DSP FW writes a 1 to this bit to
573 * indicate downstream message received is consumed. This internally causes an IOSF
574 * SB completion transaction if original downstream request is non-posted. If
575 * original message is posted then upstream completion is not generated by HW. This
576 * bit is cleared by HW.
577 */
578 #define USCPCTLSTS_SBCP BIT(31)
579
580
581 /*
582 * Upstream completion SAI
583 */
584 #define USCPSAI 0x64
585
586 /*
587 * SAI
588 * type: RO, rst: DSPISAI_2SB
589 *
590 * Completion SAI to be sent for downstream non-posted message. Reset value is
591 * hardcoded to parameter DSPISAI_2SB.
592 */
593 #define USCPSAI_CPSAI GENMASK(7, 0)
594
595 /*
596 * Reserved
597 * type: RO, rst: 00h
598 */
599 #define USCPSAI_RSVD15 GENMASK(15, 8)
600
601 /*
602 * Spare 1
603 * type: RW, rst: 0h, rst domain: gHSTRST
604 *
605 * 4 Spare bits.
606 */
607 #define USCPSAI_SPARE1 GENMASK(19, 16)
608
609 /*
610 * Reserved
611 * type: RO, rst: 000h
612 */
613 #define USCPSAI_RSVD30 GENMASK(30, 20)
614
615 /*
616 * Spare 0
617 * type: RW, rst: 0b, rst domain: gHSTRST
618 *
619 * 1 Spare bit.
620 */
621 #define USCPSAI_SPARE0 BIT(31)
622
623
624 /*
625 * SAI Width
626 */
627 #define SAIWDTH 0x68
628
629 /*
630 * SAI Width
631 * type: RO, rst: SAI_WIDTH
632 *
633 * Specifies the SAI width value.
634 * 0-based value.
635 */
636 #define SAIWDTH_SAIWDTH GENMASK(3, 0)
637
638 /*
639 * Reserved
640 * type: RO, rst: 000 0000h
641 */
642 #define SAIWDTH_RSVD31 GENMASK(31, 4)
643
644
645 /*
646 * Side Clock Gate
647 * Sideband clock gating enable register.
648 */
649 #define SCLKG 0x6C
650
651 /*
652 * Local Clock Gate
653 * type: RW, rst: 0b, rst domain: gHSTRST
654 *
655 * 0: Clk is un-gated
656 * 1: Clk is gated
657 * Implementation Note: Local clock gating is not implemented as there are only ~10
658 * flops in the design.
659 */
660 #define SCLKG_LCG BIT(0)
661
662 /*
663 * Trunk Clock Gate
664 * type: RW, rst: 0b, rst domain: gHSTRST
665 *
666 * 0: Clk request enabled
667 * 1: Clk is gated
668 * Implementation Note: This FW managed TCG bit is not used as HW has been improved
669 * to support trunk clock gating based on FSM operation.
670 */
671 #define SCLKG_TCG BIT(1)
672
673 /*
674 * Reserved
675 * type: RO, rst: 0000 0000h
676 */
677 #define SCLKG_RSVD31 GENMASK(31, 2)
678
679
680 /*
681 * Downstream Data 2
682 * Receive data (second DW) register for downstream message.
683 *
684 * type: RW, rst: 0000 0000h, rst domain: gHSTRST
685 *
686 * Data received in message. Second DW, if valid.
687 */
688 #define DSDATA2 0x74
689
690
691 /*
692 * Downstream Access Enable
693 *
694 * Note: boot prep handling is an artifact of re-using the component from ISH. There is no usage
695 * model in ACE IP to support any boot prep message handling by FW.
696 */
697 #define DSACCEN 0x80
698
699 /*
700 * Access Enable
701 * type: RW, rst: 0b, rst domain: gHSTRST
702 *
703 * This bit is set by DSP FW to enable SBEP HW to accept downstream cycles from
704 * Sideband peer agents (as well as access control policy owner for survivability).
705 * NOTE: If a BOOTPREP message is received, DSP FW is interrupted unconditionally,
706 * i.e. irrespective of this bit being 1 or 0.
707 */
708 #define DSACCEN_ACCEN BIT(0)
709
710 /*
711 * Reserved
712 * type: RO, rst: 0000 0000h
713 */
714 #define DSACCEN_RSVD31 GENMASK(31, 1)
715
716
717 /*
718 * Boot Prep Control
719 * Boot prep message control register.
720 * Note: boot prep handling is an artifact of re-using the component from ISH. There is no usage
721 * model in ACE IP to support any boot prep message handling by FW.
722 */
723 #define BPCTL 0x84
724
725 /*
726 * type: RW/1C, rst: 0b, rst domain: gHSTRST
727 * Boot Prep Received Status
728 *
729 * This bit is set by SBEP HW upon the reception of BOOTPREP message. DSP FW is
730 * required to clear this status bit by writing a 0 to the bit, upon issuing
731 * BOOTPREPACK message on the upstream path of SBEP HW. SBEP HW will clear this bit,
732 * upon auto ack'ing of BOOTPREP due to timeout condition.
733 */
734 #define BPCTL_BPRCVSTS BIT(0)
735
736 /*
737 * Reserved
738 * type: RO, rst: 0000 0000h
739 */
740 #define BPCTL_RSVD31 GENMASK(31, 1)
741
742
743 #define CW_TRANSACTION_NONPOSTED 0
744 #define CW_TRANSACTION_POSTED 1
745
746 #define CW_TRANSACTION_WRITE 0
747 #define CW_TRANSACTION_READ 1
748
749 /*
750 * @brief Check the endpoint state machine is idle
751 *
752 * @retval false The Endpoint State Machine is busy
753 * @retval true The Endpoint State Machine is idle
754 */
cw_upstream_ready(void)755 static inline bool cw_upstream_ready(void)
756 {
757 uint32_t status = sys_read32(CW_BASE + USSTS);
758
759 status &= ~USSTS_SMSTS;
760 sys_write32(status, CW_BASE + USSTS);
761 return !(sys_read32(CW_BASE + USSTS) & USSTS_SMSTS);
762 }
763
764 /*
765 * @brief Configure attributes of upstream message
766 *
767 * @param dest Destination Port ID for message to be sent.
768 * @param func Function ID for register access to be sent.
769 * @param opcode Opcode for message to be sent.
770 * @param be Byte enables for message to be sent.
771 * @param bar Base Address Register for register access to be sent.
772 */
cw_upstream_set_attr(uint32_t dest,uint32_t func,uint32_t opcode,uint32_t be,uint32_t bar)773 static inline void cw_upstream_set_attr(uint32_t dest, uint32_t func, uint32_t opcode,
774 uint32_t be, uint32_t bar)
775 {
776 uint32_t attr = FIELD_PREP(USATTR_DSTPID, dest) | FIELD_PREP(USATTR_FID, func) |
777 FIELD_PREP(USATTR_OPC, opcode) | FIELD_PREP(USATTR_BE, be) |
778 FIELD_PREP(USATTR_BAR, bar);
779 sys_write32(attr, CW_BASE + USATTR);
780 }
781
782 /*
783 * @brief Set 16bit address for upstream message.
784 *
785 * @param address Address for message to be sent.
786 */
cw_upstream_set_address16(uint16_t address)787 static inline void cw_upstream_set_address16(uint16_t address)
788 {
789 sys_write32(address, CW_BASE + USLADDR);
790 sys_write32(0, CW_BASE + USUADDR);
791 }
792
793 /*
794 * @brief Set transmit data for upstream message.
795 *
796 * @param data Data for message to be sent.
797 */
cw_upstream_set_data(uint32_t data)798 static inline void cw_upstream_set_data(uint32_t data)
799 {
800 sys_write32(data, CW_BASE + USDATA);
801 }
802
803 /*
804 * @brief Interrupt enable / disable for message sent interrupt.
805 *
806 * @param enable Interrupt state
807 */
cw_upstream_enable_sent_intr(bool enable)808 static inline void cw_upstream_enable_sent_intr(bool enable)
809 {
810 uint32_t cmd = sys_read32(CW_BASE + USCMD);
811
812 if (enable)
813 cmd |= USCMD_IE;
814 else
815 cmd &= ~USCMD_IE;
816
817 sys_write32(cmd, CW_BASE + USCMD);
818 }
819
820 /*
821 * @brief Write posted message.
822 */
cw_upstream_do_pw(void)823 static inline void cw_upstream_do_pw(void)
824 {
825 uint32_t cmd = sys_read32(CW_BASE + USCMD);
826
827 cmd &= ~(USCMD_MSGTYP | USCMD_TRANTYP);
828 cmd |= FIELD_PREP(USCMD_MSGTYP, CW_TRANSACTION_POSTED) |
829 FIELD_PREP(USCMD_TRANTYP, CW_TRANSACTION_WRITE) |
830 USCMD_SSBTRAN;
831
832 sys_write32(cmd, CW_BASE + USCMD);
833 }
834
835 /*
836 * @brief Clear message send interrupt status
837 */
cw_upstream_clear_msgsent(void)838 static inline void cw_upstream_clear_msgsent(void)
839 {
840 uint32_t sts = sys_read32(CW_BASE + USSTS);
841
842 sts |= USSTS_MSGSENT;
843 sys_write32(sts, CW_BASE + USSTS);
844 }
845
846 /*
847 * @brief Wait for message to be send.
848 */
cw_upstream_wait_for_sent(void)849 static inline void cw_upstream_wait_for_sent(void)
850 {
851 WAIT_FOR(sys_read32(CW_BASE + USSTS) & USSTS_MSGSENT, 100, k_busy_wait(1));
852
853 cw_upstream_clear_msgsent();
854 }
855
856 /*
857 * @brief Write a sideband message.
858 */
859 void cw_sb_write(uint32_t dest, uint32_t func, uint16_t address, uint32_t data);
860
861
862 #endif /* INTEL_COMM_WIDGET_H */
863
