Searched refs:DMICLCTL_OFFSET (Results 1 – 6 of 6) sorted by relevance
139 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | in dai_dmic_claim_ownership()140 FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_claim_ownership()146 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & in dai_dmic_release_ownership()147 ~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_release_ownership()290 sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD), in dai_dmic_dis_clk_gating()291 dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_dis_clk_gating()302 sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD), in dai_dmic_en_clk_gating()303 dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_en_clk_gating()328 sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA), in dai_dmic_en_power()329 base + DMICLCTL_OFFSET); in dai_dmic_en_power()[all …]
288 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()291 sys_write32(val, dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()307 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_get()
28 #define DMICLCTL_OFFSET 0x04 macro
26 #define DMICLCTL_OFFSET 0x04 macro
134 #define DMICLCTL_OFFSET 0x04 macro
335 #define DMICLCTL_OFFSET 0x04 macro
