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Searched refs:CLKMGR_PLLGLOB_RST_SET_MSK (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_agilex5_ll.h93 #define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002U macro
/Zephyr-Core-3.7.0/include/zephyr/drivers/clock_control/
Dclock_agilex_ll.h109 #define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 macro