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Searched refs:CLKMGR_PLLGLOB_REFCLKDIV (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_agilex5_ll.h95 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003F00) >> 8) macro
/Zephyr-Core-3.7.0/include/zephyr/drivers/clock_control/
Dclock_agilex_ll.h111 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) macro