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Searched refs:CLKMGR_PERPLL_PLLC0 (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_agilex5_ll.h51 #define CLKMGR_PERPLL_PLLC0 0x34 macro
Dclock_agilex_ll.c101 CLKMGR_PERPLL_PLLC0); in get_mpu_clk()
Dclock_control_agilex5_ll.c131 mpu_clk = get_clk_freq(CLKMGR_MAINPLL_MPUCLK, CLKMGR_MAINPLL_PLLC0, CLKMGR_PERPLL_PLLC0); in get_mpu_clk()
/Zephyr-Core-3.7.0/include/zephyr/drivers/clock_control/
Dclock_agilex_ll.h48 #define CLKMGR_PERPLL_PLLC0 0x30 macro