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Searched refs:CLKMGR_MAINPLL_OFFSET (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_agilex5_ll.h20 #define CLKMGR_MAINPLL_OFFSET 0x24 macro
Dclock_control_agilex5_ll.c33 clock_agilex5_ll.mainpll_addr = clock_agilex5_ll.base_addr + CLKMGR_MAINPLL_OFFSET; in clock_agilex5_ll_init()