1 /*
2  * Copyright (c) 2019 Intel Corporation.
3  * Copyright (c) 2023 Microchip Technology Inc.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #define DT_DRV_COMPAT microchip_xec_adc
9 
10 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
11 #include <zephyr/logging/log.h>
12 LOG_MODULE_REGISTER(adc_mchp_xec);
13 
14 #include <zephyr/drivers/adc.h>
15 #ifdef CONFIG_SOC_SERIES_MEC172X
16 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
17 #endif
18 #include <zephyr/drivers/pinctrl.h>
19 #include <zephyr/pm/device.h>
20 #include <zephyr/pm/policy.h>
21 #include <soc.h>
22 #include <errno.h>
23 #include <zephyr/irq.h>
24 
25 #define ADC_CONTEXT_USES_KERNEL_TIMER
26 #include "adc_context.h"
27 
28 #define XEC_ADC_VREF_ANALOG 3300
29 
30 /* ADC Control Register */
31 #define XEC_ADC_CTRL_SINGLE_DONE_STATUS		BIT(7)
32 #define XEC_ADC_CTRL_REPEAT_DONE_STATUS		BIT(6)
33 #define XER_ADC_CTRL_SOFT_RESET			BIT(4)
34 #define XEC_ADC_CTRL_POWER_SAVER_DIS		BIT(3)
35 #define XEC_ADC_CTRL_START_REPEAT		BIT(2)
36 #define XEC_ADC_CTRL_START_SINGLE		BIT(1)
37 #define XEC_ADC_CTRL_ACTIVATE			BIT(0)
38 
39 /* ADC implements two interrupt signals:
40  * One-shot(single) conversion of a set of channels
41  * Repeat conversion of a set of channels
42  * Channel sets for single and repeat may be different.
43  */
44 enum adc_pm_policy_state_flag {
45 	ADC_PM_POLICY_STATE_SINGLE_FLAG,
46 	ADC_PM_POLICY_STATE_REPEAT_FLAG,
47 	ADC_PM_POLICY_STATE_FLAG_COUNT,
48 };
49 
50 
51 struct adc_xec_regs {
52 	uint32_t control_reg;
53 	uint32_t delay_reg;
54 	uint32_t status_reg;
55 	uint32_t single_reg;
56 	uint32_t repeat_reg;
57 	uint32_t channel_read_reg[8];
58 	uint32_t unused[18];
59 	uint32_t config_reg;
60 	uint32_t vref_channel_reg;
61 	uint32_t vref_control_reg;
62 	uint32_t sar_control_reg;
63 };
64 
65 struct adc_xec_config {
66 	struct adc_xec_regs *regs;
67 
68 	uint8_t girq_single;
69 	uint8_t girq_single_pos;
70 	uint8_t girq_repeat;
71 	uint8_t girq_repeat_pos;
72 	uint8_t pcr_regidx;
73 	uint8_t pcr_bitpos;
74 	const struct pinctrl_dev_config *pcfg;
75 };
76 
77 struct adc_xec_data {
78 	struct adc_context ctx;
79 	const struct device *adc_dev;
80 	uint16_t *buffer;
81 	uint16_t *repeat_buffer;
82 #ifdef CONFIG_PM_DEVICE
83 	ATOMIC_DEFINE(pm_policy_state_flag, ADC_PM_POLICY_STATE_FLAG_COUNT);
84 #endif
85 };
86 
87 #ifdef CONFIG_PM_DEVICE
adc_xec_pm_policy_state_lock_get(struct adc_xec_data * data,enum adc_pm_policy_state_flag flag)88 static void adc_xec_pm_policy_state_lock_get(struct adc_xec_data *data,
89 					       enum adc_pm_policy_state_flag flag)
90 {
91 	if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
92 		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
93 	}
94 }
95 
adc_xec_pm_policy_state_lock_put(struct adc_xec_data * data,enum adc_pm_policy_state_flag flag)96 static void adc_xec_pm_policy_state_lock_put(struct adc_xec_data *data,
97 					    enum adc_pm_policy_state_flag flag)
98 {
99 	if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
100 		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
101 	}
102 }
103 #endif
104 
adc_context_start_sampling(struct adc_context * ctx)105 static void adc_context_start_sampling(struct adc_context *ctx)
106 {
107 	struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
108 	const struct device *adc_dev = data->adc_dev;
109 	const struct adc_xec_config * const devcfg = adc_dev->config;
110 	struct adc_xec_regs *regs = devcfg->regs;
111 
112 	data->repeat_buffer = data->buffer;
113 
114 #ifdef CONFIG_PM_DEVICE
115 	adc_xec_pm_policy_state_lock_get(data, ADC_PM_POLICY_STATE_SINGLE_FLAG);
116 #endif
117 	regs->single_reg = ctx->sequence.channels;
118 	regs->control_reg |= XEC_ADC_CTRL_START_SINGLE;
119 }
120 
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)121 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
122 					      bool repeat_sampling)
123 {
124 	struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
125 
126 	if (repeat_sampling) {
127 		data->buffer = data->repeat_buffer;
128 	}
129 }
130 
adc_xec_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)131 static int adc_xec_channel_setup(const struct device *dev,
132 				 const struct adc_channel_cfg *channel_cfg)
133 {
134 	const struct adc_xec_config *const cfg = dev->config;
135 	struct adc_xec_regs * const regs = cfg->regs;
136 	uint32_t areg;
137 
138 	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
139 		return -EINVAL;
140 	}
141 
142 	if (channel_cfg->channel_id >= MCHP_ADC_MAX_CHAN) {
143 		return -EINVAL;
144 	}
145 
146 	if (channel_cfg->gain != ADC_GAIN_1) {
147 		return -EINVAL;
148 	}
149 
150 	/* Setup VREF */
151 	areg = regs->vref_channel_reg;
152 	areg &= ~MCHP_ADC_CH_VREF_SEL_MASK(channel_cfg->channel_id);
153 
154 	if (channel_cfg->reference == ADC_REF_INTERNAL) {
155 		areg |= MCHP_ADC_CH_VREF_SEL_PAD(channel_cfg->channel_id);
156 	} else if (channel_cfg->reference == ADC_REF_EXTERNAL0) {
157 		areg |= MCHP_ADC_CH_VREF_SEL_GPIO(channel_cfg->channel_id);
158 	} else {
159 		return -EINVAL;
160 	}
161 
162 	regs->vref_channel_reg = areg;
163 
164 	/* Differential mode? */
165 	areg = regs->sar_control_reg;
166 	areg &= ~BIT(MCHP_ADC_SAR_CTRL_SELDIFF_POS);
167 	if (channel_cfg->differential != 0) {
168 		areg |= MCHP_ADC_SAR_CTRL_SELDIFF_EN;
169 	}
170 	regs->sar_control_reg = areg;
171 
172 	return 0;
173 }
174 
adc_xec_validate_buffer_size(const struct adc_sequence * sequence)175 static bool adc_xec_validate_buffer_size(const struct adc_sequence *sequence)
176 {
177 	int chan_count = 0;
178 	size_t buff_need;
179 	uint32_t chan_mask;
180 
181 	for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
182 		if (chan_mask & sequence->channels) {
183 			chan_count++;
184 		}
185 	}
186 
187 	buff_need = chan_count * sizeof(uint16_t);
188 
189 	if (sequence->options) {
190 		buff_need *= 1 + sequence->options->extra_samplings;
191 	}
192 
193 	if (buff_need > sequence->buffer_size) {
194 		return false;
195 	}
196 
197 	return true;
198 }
199 
adc_xec_start_read(const struct device * dev,const struct adc_sequence * sequence)200 static int adc_xec_start_read(const struct device *dev,
201 			      const struct adc_sequence *sequence)
202 {
203 	const struct adc_xec_config *const cfg = dev->config;
204 	struct adc_xec_regs * const regs = cfg->regs;
205 	struct adc_xec_data * const data = dev->data;
206 	uint32_t sar_ctrl;
207 
208 	if (sequence->channels & ~BIT_MASK(MCHP_ADC_MAX_CHAN)) {
209 		LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
210 		return -EINVAL;
211 	}
212 
213 	if (sequence->channels == 0UL) {
214 		LOG_ERR("No channel selected");
215 		return -EINVAL;
216 	}
217 
218 	if (!adc_xec_validate_buffer_size(sequence)) {
219 		LOG_ERR("Incorrect buffer size");
220 		return -ENOMEM;
221 	}
222 
223 	/* Setup ADC resolution */
224 	sar_ctrl = regs->sar_control_reg;
225 	sar_ctrl &= ~(MCHP_ADC_SAR_CTRL_RES_MASK |
226 		      (1 << MCHP_ADC_SAR_CTRL_SHIFTD_POS));
227 
228 	if (sequence->resolution == 12) {
229 		sar_ctrl |= MCHP_ADC_SAR_CTRL_RES_12_BITS;
230 	} else if (sequence->resolution == 10) {
231 		sar_ctrl |= MCHP_ADC_SAR_CTRL_RES_10_BITS;
232 		sar_ctrl |= MCHP_ADC_SAR_CTRL_SHIFTD_EN;
233 	} else {
234 		return -EINVAL;
235 	}
236 
237 	regs->sar_control_reg = sar_ctrl;
238 
239 	data->buffer = sequence->buffer;
240 
241 	adc_context_start_read(&data->ctx, sequence);
242 
243 	return adc_context_wait_for_completion(&data->ctx);
244 }
245 
adc_xec_read(const struct device * dev,const struct adc_sequence * sequence)246 static int adc_xec_read(const struct device *dev,
247 			const struct adc_sequence *sequence)
248 {
249 	struct adc_xec_data * const data = dev->data;
250 	int error;
251 
252 	adc_context_lock(&data->ctx, false, NULL);
253 	error = adc_xec_start_read(dev, sequence);
254 	adc_context_release(&data->ctx, error);
255 
256 	return error;
257 }
258 
259 #ifdef CONFIG_ADC_ASYNC
adc_xec_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)260 static int adc_xec_read_async(const struct device *dev,
261 			      const struct adc_sequence *sequence,
262 			      struct k_poll_signal *async)
263 {
264 	struct adc_xec_data * const data = dev->data;
265 	int error;
266 
267 	adc_context_lock(&data->ctx, true, async);
268 	error = adc_xec_start_read(dev, sequence);
269 	adc_context_release(&data->ctx, error);
270 
271 	return error;
272 }
273 #endif /* CONFIG_ADC_ASYNC */
274 
xec_adc_get_sample(const struct device * dev)275 static void xec_adc_get_sample(const struct device *dev)
276 {
277 	const struct adc_xec_config *const cfg = dev->config;
278 	struct adc_xec_regs * const regs = cfg->regs;
279 	struct adc_xec_data * const data = dev->data;
280 	uint32_t idx;
281 	uint32_t channels = regs->status_reg;
282 	uint32_t ch_status = channels;
283 	uint32_t bit;
284 
285 	/*
286 	 * Using the enabled channel bit set, from
287 	 * lowest channel number to highest, find out
288 	 * which channel is enabled and copy the ADC
289 	 * values from hardware registers to the data
290 	 * buffer.
291 	 */
292 	bit = find_lsb_set(channels);
293 	while (bit != 0) {
294 		idx = bit - 1;
295 
296 		*data->buffer = (uint16_t)regs->channel_read_reg[idx];
297 		data->buffer++;
298 
299 		channels &= ~BIT(idx);
300 		bit = find_lsb_set(channels);
301 	}
302 
303 	/* Clear the status register */
304 	regs->status_reg = ch_status;
305 }
306 
307 #ifdef CONFIG_SOC_SERIES_MEC172X
adc_xec_girq_clr(uint8_t girq_idx,uint8_t girq_posn)308 static inline void adc_xec_girq_clr(uint8_t girq_idx, uint8_t girq_posn)
309 {
310 	mchp_xec_ecia_girq_src_clr(girq_idx, girq_posn);
311 }
312 
adc_xec_girq_en(uint8_t girq_idx,uint8_t girq_posn)313 static inline void adc_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
314 {
315 	mchp_xec_ecia_girq_src_en(girq_idx, girq_posn);
316 }
317 
adc_xec_girq_dis(uint8_t girq_idx,uint8_t girq_posn)318 static inline void adc_xec_girq_dis(uint8_t girq_idx, uint8_t girq_posn)
319 {
320 	mchp_xec_ecia_girq_src_dis(girq_idx, girq_posn);
321 }
322 #else
323 
adc_xec_girq_clr(uint8_t girq_idx,uint8_t girq_posn)324 static inline void adc_xec_girq_clr(uint8_t girq_idx, uint8_t girq_posn)
325 {
326 	MCHP_GIRQ_SRC(girq_idx) = BIT(girq_posn);
327 }
328 
adc_xec_girq_en(uint8_t girq_idx,uint8_t girq_posn)329 static inline void adc_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
330 {
331 	MCHP_GIRQ_ENSET(girq_idx) = BIT(girq_posn);
332 }
333 
adc_xec_girq_dis(uint8_t girq_idx,uint8_t girq_posn)334 static inline void adc_xec_girq_dis(uint8_t girq_idx, uint8_t girq_posn)
335 {
336 	MCHP_GIRQ_ENCLR(girq_idx) = MCHP_KBC_IBF_GIRQ;
337 }
338 #endif
339 
adc_xec_single_isr(const struct device * dev)340 static void adc_xec_single_isr(const struct device *dev)
341 {
342 	const struct adc_xec_config *const cfg = dev->config;
343 	struct adc_xec_regs * const regs = cfg->regs;
344 	struct adc_xec_data * const data = dev->data;
345 	uint32_t ctrl;
346 
347 	/* Clear START_SINGLE bit and clear SINGLE_DONE_STATUS */
348 	ctrl = regs->control_reg;
349 	ctrl &= ~XEC_ADC_CTRL_START_SINGLE;
350 	ctrl |= XEC_ADC_CTRL_SINGLE_DONE_STATUS;
351 	regs->control_reg = ctrl;
352 
353 	/* Also clear GIRQ source status bit */
354 	adc_xec_girq_clr(cfg->girq_single, cfg->girq_single_pos);
355 
356 	xec_adc_get_sample(dev);
357 
358 #ifdef CONFIG_PM_DEVICE
359 	adc_xec_pm_policy_state_lock_put(data, ADC_PM_POLICY_STATE_SINGLE_FLAG);
360 #endif
361 
362 	adc_context_on_sampling_done(&data->ctx, dev);
363 
364 	LOG_DBG("ADC ISR triggered.");
365 }
366 
367 
368 #ifdef CONFIG_PM_DEVICE
adc_xec_pm_action(const struct device * dev,enum pm_device_action action)369 static int adc_xec_pm_action(const struct device *dev, enum pm_device_action action)
370 {
371 	const struct adc_xec_config *const devcfg = dev->config;
372 	struct adc_xec_regs * const adc_regs = devcfg->regs;
373 	int ret;
374 
375 	switch (action) {
376 	case PM_DEVICE_ACTION_RESUME:
377 		ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
378 		/* ADC activate  */
379 		adc_regs->control_reg |= XEC_ADC_CTRL_ACTIVATE;
380 		break;
381 	case PM_DEVICE_ACTION_SUSPEND:
382 		/* ADC deactivate  */
383 		adc_regs->control_reg &= ~(XEC_ADC_CTRL_ACTIVATE);
384 		/* If application does not want to turn off ADC pins it will
385 		 * not define pinctrl-1 for this node.
386 		 */
387 		ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP);
388 		if (ret == -ENOENT) { /* pinctrl-1 does not exist.  */
389 			ret = 0;
390 		}
391 		break;
392 	default:
393 		ret = -ENOTSUP;
394 	}
395 
396 	return ret;
397 }
398 #endif /* CONFIG_PM_DEVICE */
399 
400 struct adc_driver_api adc_xec_api = {
401 	.channel_setup = adc_xec_channel_setup,
402 	.read = adc_xec_read,
403 #if defined(CONFIG_ADC_ASYNC)
404 	.read_async = adc_xec_read_async,
405 #endif
406 	.ref_internal = XEC_ADC_VREF_ANALOG,
407 };
408 
409 /* ADC Config Register */
410 #define XEC_ADC_CFG_CLK_VAL(clk_time)	(		\
411 	(clk_time << MCHP_ADC_CFG_CLK_LO_TIME_POS) |	\
412 	(clk_time << MCHP_ADC_CFG_CLK_HI_TIME_POS))
413 
adc_xec_init(const struct device * dev)414 static int adc_xec_init(const struct device *dev)
415 {
416 	const struct adc_xec_config *const cfg = dev->config;
417 	struct adc_xec_regs * const regs = cfg->regs;
418 	struct adc_xec_data * const data = dev->data;
419 	int ret;
420 
421 	data->adc_dev = dev;
422 
423 	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
424 	if (ret != 0) {
425 		LOG_ERR("XEC ADC V2 pinctrl setup failed (%d)", ret);
426 		return ret;
427 	}
428 
429 	regs->config_reg = XEC_ADC_CFG_CLK_VAL(DT_INST_PROP(0, clktime));
430 
431 	regs->control_reg =  XEC_ADC_CTRL_ACTIVATE
432 		| XEC_ADC_CTRL_POWER_SAVER_DIS
433 		| XEC_ADC_CTRL_SINGLE_DONE_STATUS
434 		| XEC_ADC_CTRL_REPEAT_DONE_STATUS;
435 
436 	adc_xec_girq_dis(cfg->girq_repeat, cfg->girq_repeat_pos);
437 	adc_xec_girq_clr(cfg->girq_repeat, cfg->girq_repeat_pos);
438 	adc_xec_girq_dis(cfg->girq_single, cfg->girq_single_pos);
439 	adc_xec_girq_clr(cfg->girq_single, cfg->girq_single_pos);
440 	adc_xec_girq_en(cfg->girq_single, cfg->girq_single_pos);
441 
442 	IRQ_CONNECT(DT_INST_IRQN(0),
443 		    DT_INST_IRQ(0, priority),
444 		    adc_xec_single_isr, DEVICE_DT_INST_GET(0), 0);
445 	irq_enable(DT_INST_IRQN(0));
446 
447 	adc_context_unlock_unconditionally(&data->ctx);
448 
449 	return 0;
450 }
451 
452 PINCTRL_DT_INST_DEFINE(0);
453 
454 static struct adc_xec_config adc_xec_dev_cfg_0 = {
455 	.regs = (struct adc_xec_regs *)(DT_INST_REG_ADDR(0)),
456 	.girq_single = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)),
457 	.girq_single_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)),
458 	.girq_repeat = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 2)),
459 	.girq_repeat_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 3)),
460 	.pcr_regidx = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 0)),
461 	.pcr_bitpos = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 1)),
462 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
463 };
464 
465 static struct adc_xec_data adc_xec_dev_data_0 = {
466 	ADC_CONTEXT_INIT_TIMER(adc_xec_dev_data_0, ctx),
467 	ADC_CONTEXT_INIT_LOCK(adc_xec_dev_data_0, ctx),
468 	ADC_CONTEXT_INIT_SYNC(adc_xec_dev_data_0, ctx),
469 };
470 
471 PM_DEVICE_DT_INST_DEFINE(0, adc_xec_pm_action);
472 
473 DEVICE_DT_INST_DEFINE(0, adc_xec_init, PM_DEVICE_DT_INST_GET(0),
474 		    &adc_xec_dev_data_0, &adc_xec_dev_cfg_0,
475 		    PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY,
476 		    &adc_xec_api);
477