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Searched refs:vbr (Results 1 – 3 of 3) sorted by relevance

/Zephyr-Core-3.6.0/samples/drivers/clock_control_xec/src/
Dmain.c42 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_clock_regs() local
43 uint32_t cken = vbr->CLK32_EN; in vbat_clock_regs()
65 LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM); in vbat_clock_regs()
70 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_power_fail() local
71 uint32_t pfrs = vbr->PFRS; in vbat_power_fail()
80 vbr->PFRS = 0xffffffffU; in vbat_power_fail()
161 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_clock_regs() local
162 uint32_t vb_clk_src = vbr->CLK32_SRC; in vbat_clock_regs()
169 struct vbatr_regs *vbr = ((struct vbatr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 1)); in vbat_power_fail() local
170 uint32_t pfrs = vbr->PFRS; in vbat_power_fail()
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/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_control_mchp_xec.c282 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in soc_clk32_init() local
288 vbr->CLK32_TRIM_CTRL = XEC_CC15_TRIM_ENABLE_INT_OSCILLATOR; in soc_clk32_init()
310 if ((vbr->CLK32_SRC & 0xffU) != cken) { in soc_clk32_init()
311 vbr->CLK32_SRC = cken; in soc_clk32_init()
342 static bool is_sil_osc_enabled(struct vbatr_hw_regs *vbr) in is_sil_osc_enabled() argument
344 if (vbr->CLK32_SRC & XEC_CC_VBATR_CS_SO_EN) { in is_sil_osc_enabled()
351 static void enable_sil_osc(struct vbatr_hw_regs *vbr) in enable_sil_osc() argument
353 vbr->CLK32_SRC |= XEC_CC_VBATR_CS_SO_EN; in enable_sil_osc()
434 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in disable_32k_crystal() local
435 uint32_t vbcs = vbr->CLK32_SRC; in disable_32k_crystal()
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/Zephyr-Core-3.6.0/soc/arm/microchip_mec/mec172x/
Ddevice_power.c42 #define VBATM_XEC_ADDR DT_REG_ADDR(DT_NODELABEL(vbr))