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Searched refs:sys_write32 (Results 1 – 25 of 158) sorted by relevance

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/Zephyr-Core-3.6.0/drivers/interrupt_controller/
Dintc_gic.c43 sys_write32((1 << int_off), (GICD_ISENABLERn + int_grp * 4)); in arm_gic_irq_enable()
53 sys_write32((1 << int_off), (GICD_ICENABLERn + int_grp * 4)); in arm_gic_irq_disable()
89 sys_write32((1 << int_off), (GICD_ICPENDRn + int_grp * 4)); in arm_gic_irq_clear_pending()
111 sys_write32(val, GICD_ICFGRn + int_grp); in arm_gic_irq_set_priority()
135 sys_write32(irq, GICC_EOIR); in arm_gic_eoi()
150 sys_write32(sgi_val, GICD_SGIR); in gic_raise_sgi()
170 sys_write32(0, GICD_CTLR); in gic_dist_init()
184 sys_write32(reg_val, GICD_ITARGETSRn + i); in gic_dist_init()
191 sys_write32(0, GICD_ICFGRn + i / 4); in gic_dist_init()
196 sys_write32(0, GICD_IPRIORITYRn + i); in gic_dist_init()
[all …]
Dintc_gicv3.c118 sys_write32((uint32_t)val, addr); in arm_gic_write_irouter()
119 sys_write32((uint32_t)(val >> 32U), addr + 4); in arm_gic_write_irouter()
142 sys_write32(mask, ICENABLER(base, idx)); in arm_gic_irq_set_priority()
158 sys_write32(val, ICFGR(base, idx)); in arm_gic_irq_set_priority()
173 sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx)); in arm_gic_irq_enable()
198 sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx)); in arm_gic_irq_disable()
235 sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx)); in arm_gic_irq_clear_pending()
344 sys_write32(ctlr, rdist + GICR_CTLR); in gicv3_rdist_setup_lpis()
366 sys_write32(ctlr, rdist + GICR_CTLR); in gicv3_rdist_setup_lpis()
383 sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0)); in gicv3_cpuif_init()
[all …]
Dintc_vim.c43 sys_write32(BIT(irq_bit_num), VIM_IRQSTS(irq_group_num)); in z_vim_irq_get_active()
54 sys_write32(0, VIM_IRQVEC); in z_vim_irq_eoi()
88 sys_write32(regval, VIM_INTTYPE(irq_group_num)); in z_vim_irq_priority_set()
103 sys_write32(BIT(irq_bit_num), VIM_INTR_EN_SET(irq_group_num)); in z_vim_irq_enable()
118 sys_write32(BIT(irq_bit_num), VIM_INTR_EN_CLR(irq_group_num)); in z_vim_irq_disable()
150 sys_write32(BIT(irq_bit_num), VIM_RAW(irq_group_num)); in z_vim_arm_enter_irq()
/Zephyr-Core-3.6.0/drivers/timer/
Dxlnx_psttc_timer.c72 sys_write32(match, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in update_match()
154 sys_write32(XTTCPS_CNT_CNTRL_DIS_MASK, in sys_clock_driver_init()
163 sys_write32(XTTCPS_CNT_CNTRL_RESET_VALUE, in sys_clock_driver_init()
165 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_CLK_CNTRL_OFFSET); in sys_clock_driver_init()
166 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_INTERVAL_VAL_OFFSET); in sys_clock_driver_init()
167 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in sys_clock_driver_init()
168 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_1_OFFSET); in sys_clock_driver_init()
169 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_2_OFFSET); in sys_clock_driver_init()
170 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET); in sys_clock_driver_init()
171 sys_write32(XTTCPS_IXR_ALL_MASK, TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET); in sys_clock_driver_init()
[all …]
Drcar_cmt_timer.c69 sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
109 sys_write32(CLKEN0 | CLKEN1, TIMER_BASE_ADDR + CMCLKE); in sys_clock_driver_init()
114 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
118 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()
121 sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1 | CSR_ENABLE_INTERRUPT, in sys_clock_driver_init()
125 sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1, in sys_clock_driver_init()
129 sys_write32(CYCLES_PER_TICK, TIMER_BASE_ADDR + CMCOR0_OFFSET); in sys_clock_driver_init()
132 sys_write32(0xffffffff, TIMER_BASE_ADDR + CMCOR1_OFFSET); in sys_clock_driver_init()
138 sys_write32(0, TIMER_BASE_ADDR + CMCNT0_OFFSET); in sys_clock_driver_init()
154 sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
[all …]
/Zephyr-Core-3.6.0/drivers/gpio/
Dgpio_xlnx_ps_bank.c78 sys_write32(dirm_data, GPIO_XLNX_PS_BANK_DIRM_REG); in gpio_xlnx_ps_pin_configure()
92 sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_pin_configure()
95 sys_write32(oen_data, GPIO_XLNX_PS_BANK_OEN_REG); in gpio_xlnx_ps_pin_configure()
104 sys_write32(oen_data, GPIO_XLNX_PS_BANK_OEN_REG); in gpio_xlnx_ps_pin_configure()
105 sys_write32(dirm_data, GPIO_XLNX_PS_BANK_DIRM_REG); in gpio_xlnx_ps_pin_configure()
167 sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_set_masked()
195 sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_set_bits()
223 sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_clear_bits()
251 sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_toggle_bits()
294 sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_DIS_REG); in gpio_xlnx_ps_bank_pin_irq_configure()
[all …]
Dgpio_bcm2711.c90 sys_write32(regval, GPFSEL(data->base, group)); in gpio_bcm2711_pin_configure()
101 sys_write32(regval, GPSET(data->base, group)); in gpio_bcm2711_pin_configure()
105 sys_write32(regval, GPCLR(data->base, group)); in gpio_bcm2711_pin_configure()
121 sys_write32(regval, GPPULL(data->base, group)); in gpio_bcm2711_pin_configure()
158 sys_write32(FROM_U64(set, 0), GPSET(data->base, 0)); in gpio_bcm2711_port_set_masked_raw()
159 sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0)); in gpio_bcm2711_port_set_masked_raw()
160 sys_write32(FROM_U64(set, 1), GPSET(data->base, 1)); in gpio_bcm2711_port_set_masked_raw()
161 sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1)); in gpio_bcm2711_port_set_masked_raw()
174 sys_write32(FROM_U64(regval, 0), GPSET(data->base, 0)); in gpio_bcm2711_port_set_bits_raw()
175 sys_write32(FROM_U64(regval, 1), GPSET(data->base, 1)); in gpio_bcm2711_port_set_bits_raw()
[all …]
Dgpio_andes_atcgpio100.c119 sys_write32(pin_mask, GPIO_DSET(port)); in gpio_atcgpio100_config()
121 sys_write32(pin_mask, GPIO_DCLR(port)); in gpio_atcgpio100_config()
128 sys_write32((port_value | pin_mask), GPIO_DIR(port)); in gpio_atcgpio100_config()
145 sys_write32(DF_DEBOUNCED_SETTING, GPIO_DEBC(port)); in gpio_atcgpio100_config()
147 sys_write32((port_value | pin_mask), GPIO_DEBE(port)); in gpio_atcgpio100_config()
152 sys_write32((port_value & ~pin_mask), GPIO_DIR(port)); in gpio_atcgpio100_config()
180 sys_write32((port_value & ~mask) | (value & mask), GPIO_DOUT(port)); in gpio_atcgpio100_set_masked_raw()
190 sys_write32(pins, GPIO_DSET(port)); in gpio_atcgpio100_set_bits_raw()
197 sys_write32(pins, GPIO_DCLR(port)); in gpio_atcgpio100_clear_bits_raw()
210 sys_write32((port_value ^ pins), GPIO_DOUT(port)); in gpio_atcgpio100_toggle_bits()
[all …]
/Zephyr-Core-3.6.0/drivers/serial/
Duart_opentitan.c48 sys_write32(0u, cfg->base + UART_CTRL_REG_OFFSET); in uart_opentitan_init()
51 sys_write32(UART_FIFO_CTRL_RXRST_BIT | UART_FIFO_CTRL_TXRST_BIT, in uart_opentitan_init()
55 sys_write32(0u, cfg->base + UART_OVRD_REG_OFFSET); in uart_opentitan_init()
56 sys_write32(0u, cfg->base + UART_TIMEOUT_CTRL_REG_OFFSET); in uart_opentitan_init()
59 sys_write32(0u, cfg->base + UART_INTR_ENABLE_REG_OFFSET); in uart_opentitan_init()
62 sys_write32(0xffffffffu, cfg->base + UART_INTR_STATE_REG_OFFSET); in uart_opentitan_init()
65 sys_write32(UART_CTRL_TX_BIT | UART_CTRL_RX_BIT | in uart_opentitan_init()
93 sys_write32(c, cfg->base + UART_WDATA_REG_OFFSET); in uart_opentitan_poll_out()
/Zephyr-Core-3.6.0/soc/arc/snps_emsk/
Dsoc_config.c21 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x4); in uart_ns16550_init()
22 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x10); in uart_ns16550_init()
25 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x4); in uart_ns16550_init()
26 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x10); in uart_ns16550_init()
/Zephyr-Core-3.6.0/include/zephyr/arch/arm/cortex_a_r/
Dtimer.h58 sys_write32(ctrl, TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_set_compare()
60 sys_write32(lower, TIMER_REG_GET(TIMER_CMP_LOWER)); in arm_arch_timer_set_compare()
61 sys_write32(upper, TIMER_REG_GET(TIMER_CMP_UPPER)); in arm_arch_timer_set_compare()
65 sys_write32(ctrl, TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_set_compare()
87 sys_write32(TIMER_ISR_EVENT_FLAG, TIMER_REG_GET(TIMER_ISR)); in arm_arch_timer_clear_int_status()
103 sys_write32(ctrl, TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_enable()
115 sys_write32(1, TIMER_REG_GET(TIMER_ISR)); in arm_arch_timer_set_irq_mask()
117 sys_write32(ctrl, TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_set_irq_mask()
/Zephyr-Core-3.6.0/drivers/watchdog/
Dwdt_opentitan.c38 sys_write32(0, regs + OT_REG_WDOG_COUNT_OFFSET); in ot_aontimer_setup()
39 sys_write32(1, regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_setup()
43 sys_write32(0, regs + OT_REG_WDOG_REGWEN_OFFSET); in ot_aontimer_setup()
63 sys_write32(ctrl_val & ~BIT(0), regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_disable()
137 sys_write32((uint32_t) bark_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
138 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
147 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
149 sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
154 sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
155 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
[all …]
Dwdt_andes_atcwdt200.c122 sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr)); in wdt_counter_cb()
123 sys_write32(WDT_RESTART_NUM, WDT_RESTAR(wdt_addr)); in wdt_counter_cb()
153 sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr)); in wdt_atcwdt200_set_max_timeout()
154 sys_write32(reg, WDT_CTRL(wdt_addr)); in wdt_atcwdt200_set_max_timeout()
173 sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr)); in wdt_atcwdt200_disable()
174 sys_write32(reg, WDT_CTRL(wdt_addr)); in wdt_atcwdt200_disable()
205 sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr)); in wdt_atcwdt200_setup()
206 sys_write32(reg, WDT_CTRL(wdt_addr)); in wdt_atcwdt200_setup()
215 sys_write32(WDT_WREN_NUM, WDT_WREN(wdt_addr)); in wdt_atcwdt200_setup()
216 sys_write32(reg, WDT_CTRL(wdt_addr)); in wdt_atcwdt200_setup()
[all …]
/Zephyr-Core-3.6.0/drivers/i2c/
Di2c_xilinx_axi.c74 sys_write32(int_status & I2C_XILINX_AXI_TARGET_INTERRUPTS, config->base + REG_ISR); in i2c_xilinx_axi_target_register()
77 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_target_register()
80 sys_write32(int_enable, config->base + REG_IER); in i2c_xilinx_axi_target_register()
82 sys_write32(cfg->address << 1, config->base + REG_ADR); in i2c_xilinx_axi_target_register()
83 sys_write32(0, config->base + REG_RX_FIFO_PIRQ); in i2c_xilinx_axi_target_register()
116 sys_write32(0, config->base + REG_ADR); in i2c_xilinx_axi_target_unregister()
118 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_target_unregister()
121 sys_write32(int_enable, config->base + REG_IER); in i2c_xilinx_axi_target_unregister()
154 sys_write32(read_byte, config->base + REG_TX_FIFO); in i2c_xilinx_axi_target_isr()
163 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_target_isr()
[all …]
Di2c_andes_atciic100.c54 sys_write32(reg, I2C_CMD(dev)); in i2c_atciic100_default_control()
77 sys_write32(0x0, I2C_SET(dev)); in i2c_atciic100_default_control()
86 sys_write32(reg, I2C_SET(dev)); in i2c_atciic100_default_control()
139 sys_write32(reg, I2C_SET(dev)); in i2c_atciic100_configure()
219 sys_write32(reg, I2C_INTE(dev)); in i2c_atciic100_controller_send()
224 sys_write32(reg, I2C_SET(dev)); in i2c_atciic100_controller_send()
235 sys_write32(reg, I2C_CMD(dev)); in i2c_atciic100_controller_send()
260 sys_write32(reg, I2C_CTRL(dev)); in i2c_atciic100_controller_send()
272 sys_write32(reg, I2C_ADDR(dev)); in i2c_atciic100_controller_send()
291 sys_write32(reg, I2C_INTE(dev)); in i2c_atciic100_controller_send()
[all …]
/Zephyr-Core-3.6.0/soc/riscv/opentitan/
Dsoc.c32 sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET); in soc_opentitan_init()
34 sys_write32(1u, PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET); in soc_opentitan_init()
40 sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET); in soc_opentitan_init()
42 sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET); in soc_opentitan_init()
/Zephyr-Core-3.6.0/drivers/counter/
Dcounter_andes_atcpit100.c116 sys_write32(int_enable, PIT_INTE(dev)); in atcpit100_irq_handler()
117 sys_write32(ch_enable, PIT_CHEN(dev)); in atcpit100_irq_handler()
120 sys_write32(int_status, PIT_ISTA(dev)); in atcpit100_irq_handler()
129 sys_write32(0, PIT_CHEN(dev)); in counter_atcpit100_init()
133 sys_write32(reg, PIT_CH_CTRL(dev, 0)); in counter_atcpit100_init()
134 sys_write32(reg, PIT_CH_CTRL(dev, 1)); in counter_atcpit100_init()
135 sys_write32(reg, PIT_CH_CTRL(dev, 2)); in counter_atcpit100_init()
136 sys_write32(reg, PIT_CH_CTRL(dev, 3)); in counter_atcpit100_init()
139 sys_write32(0, PIT_INTE(dev)); in counter_atcpit100_init()
140 sys_write32(UINT32_MAX, PIT_ISTA(dev)); in counter_atcpit100_init()
[all …]
/Zephyr-Core-3.6.0/drivers/pinctrl/
Dpinctrl_imx.c37 sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | in pinctrl_configure_pins()
41 sys_write32(IOMUXC1_SELECT_INPUT_DAISY(input_daisy), in pinctrl_configure_pins()
45 sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)), in pinctrl_configure_pins()
49 sys_write32( in pinctrl_configure_pins()
54 sys_write32(IOMUXC_SELECT_INPUT_DAISY(input_daisy), in pinctrl_configure_pins()
58 sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)), in pinctrl_configure_pins()
/Zephyr-Core-3.6.0/soc/arm/aspeed/ast10x0/
Dsoc.c54 sys_write32(BIT_WDT_SOC(x), event_log_reg); \
58 sys_write32(BIT_WDT_FULL(x), event_log_reg); \
62 sys_write32(BIT_WDT_ARM(x), event_log_reg); \
66 sys_write32(BIT_WDT_SW(x), event_log_reg); \
95 sys_write32(jtag_pinmux, base + JTAG_PINMUX_REG); in z_arm_platform_init()
134 sys_write32(rest1, SYS_RESET_LOG_REG1); in aspeed_print_sysrst_info()
143 sys_write32(SYS_FLASH_ABR_RESET, SYS_RESET_LOG_REG1); in aspeed_print_sysrst_info()
148 sys_write32(SYS_EXT_RESET, SYS_RESET_LOG_REG1); in aspeed_print_sysrst_info()
/Zephyr-Core-3.6.0/soc/arm/ti_k3/am62x_m4/
Dsoc.c54 sys_write32(KICK0_UNLOCK_VAL, kickAddr); /* KICK 0 */ in mmr_unlock()
56 sys_write32(KICK1_UNLOCK_VAL, kickAddr); /* KICK 1 */ in mmr_unlock()
60 sys_write32(KICK0_UNLOCK_VAL, kickAddr); /* KICK 0 */ in mmr_unlock()
62 sys_write32(KICK1_UNLOCK_VAL, kickAddr); /* KICK 1 */ in mmr_unlock()
/Zephyr-Core-3.6.0/drivers/dma/
Ddma_andes_atcdmac300.c159 sys_write32(int_status, DMA_INT_STATUS(dev)); in dma_atcdmac300_isr()
290 sys_write32(0, DMA_CH_CTRL(dev, channel)); in dma_atcdmac300_config()
294 sys_write32(DMA_INT_STATUS_CH_MSK(channel), DMA_INT_STATUS(dev)); in dma_atcdmac300_config()
298 sys_write32(tfr_size, DMA_CH_TRANSIZE(dev, channel)); in dma_atcdmac300_config()
311 sys_write32(ch_ctrl, DMA_CH_CTRL(dev, channel)); in dma_atcdmac300_config()
314 sys_write32(cfg_blocks->source_address, in dma_atcdmac300_config()
316 sys_write32(0, DMA_CH_SRC_ADDR_H(dev, channel)); in dma_atcdmac300_config()
317 sys_write32(cfg_blocks->dest_address, in dma_atcdmac300_config()
319 sys_write32(0, DMA_CH_DST_ADDR_H(dev, channel)); in dma_atcdmac300_config()
324 sys_write32((uint32_t)((long)&dma_chain[channel][current_block_idx]), in dma_atcdmac300_config()
[all …]
/Zephyr-Core-3.6.0/drivers/ethernet/
Deth_xlnx_gem.c200 sys_write32(reg_val, dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
293 sys_write32(ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT, in eth_xlnx_gem_isr()
295 sys_write32(ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT, in eth_xlnx_gem_isr()
304 sys_write32(ETH_XLNX_GEM_IXR_FRAME_RX_BIT, in eth_xlnx_gem_isr()
306 sys_write32(ETH_XLNX_GEM_IXR_FRAME_RX_BIT, in eth_xlnx_gem_isr()
324 sys_write32((0xFFFFFFFF & ~(ETH_XLNX_GEM_IXR_FRAME_RX_BIT | in eth_xlnx_gem_isr()
396 sys_write32(ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT, in eth_xlnx_gem_send()
409 sys_write32(ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT, in eth_xlnx_gem_send()
428 sys_write32(ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT, in eth_xlnx_gem_send()
452 sys_write32(reg_val, reg_ctrl); in eth_xlnx_gem_send()
[all …]
Deth_stellaris.c33 sys_write32(value, REG_MACIA0); in eth_stellaris_assign_mac()
38 sys_write32(value, REG_MACIA1); in eth_stellaris_assign_mac()
46 sys_write32(dev_data->tx_word, REG_MACDATA); in eth_stellaris_flush()
59 sys_write32(dev_data->tx_word, REG_MACDATA); in eth_stellaris_send_byte()
91 sys_write32(BIT_MACTR_NEWTX, REG_MACTR); in eth_stellaris_send()
116 sys_write32(0x0, REG_MACRCTL); in eth_stellaris_rx_error()
117 sys_write32(BIT_MACRCTL_RSTFIFO, REG_MACRCTL); in eth_stellaris_rx_error()
119 sys_write32(val, REG_MACRCTL); in eth_stellaris_rx_error()
240 sys_write32(isr_val, REG_MACRIS); in eth_stellaris_isr()
310 sys_write32(value, REG_MACRCTL); in eth_stellaris_dev_init()
[all …]
/Zephyr-Core-3.6.0/drivers/sdhc/
Dsdhc_cdns_ll.c51 sys_write32(phy_reg_addr_value, phy_reg_addr); in sdhc_cdns_write_phy_reg()
54 sys_write32(phy_reg_data_value, phy_reg_data); in sdhc_cdns_write_phy_reg()
102 sys_write32(BUS_VOLTAGE_3_3_V, in sdhc_cdns_vol_reset()
109 sys_write32(BUS_VOLTAGE_3_3_V | CDNS_SRS10_BP, in sdhc_cdns_vol_reset()
242 sys_write32(cdns_params.combophy + PHY_CTRL_REG, cdns_params.reg_base in sdhc_cdns_program_phy_reg()
248 sys_write32(value, cdns_params.reg_base + SDHC_CDNS_HRS05); in sdhc_cdns_program_phy_reg()
254 sys_write32(value, cdns_params.reg_base + SDHC_CDNS_HRS09); in sdhc_cdns_program_phy_reg()
346 sys_write32((uint32_t)desc_base, cdns_params.reg_base + SDHC_CDNS_SRS22); in sdhc_cdns_prepare()
347 sys_write32((uint32_t)(desc_base >> 32), cdns_params.reg_base + SDHC_CDNS_SRS23); in sdhc_cdns_prepare()
351 sys_write32((data->block_size << CDNS_SRS01_BLK_SIZE | in sdhc_cdns_prepare()
[all …]
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/
Dcomm_widget.h760 sys_write32(status, CW_BASE + USSTS); in cw_upstream_ready()
779 sys_write32(attr, CW_BASE + USATTR); in cw_upstream_set_attr()
789 sys_write32(address, CW_BASE + USLADDR); in cw_upstream_set_address16()
790 sys_write32(0, CW_BASE + USUADDR); in cw_upstream_set_address16()
800 sys_write32(data, CW_BASE + USDATA); in cw_upstream_set_data()
817 sys_write32(cmd, CW_BASE + USCMD); in cw_upstream_enable_sent_intr()
832 sys_write32(cmd, CW_BASE + USCMD); in cw_upstream_do_pw()
843 sys_write32(sts, CW_BASE + USSTS); in cw_upstream_clear_msgsent()

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