Home
last modified time | relevance | path

Searched refs:sys_set_bits (Results 1 – 17 of 17) sorted by relevance

/Zephyr-Core-3.6.0/drivers/sdhc/
Dsdhc_cdns_ll.c382 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_HRS09, CDNS_HRS09_RDCMD_EN_BIT | in sdhc_cdns_host_set_clk()
519 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_HRS09, CDNS_HRS09_RDCMD_EN_BIT | in sdhc_cdns_set_clk()
607 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS10, SRS10_VAL_SW); in sdhc_cdns_send_cmd()
608 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_VAL_GEN); in sdhc_cdns_send_cmd()
609 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS15, SRS15_VAL_GEN); in sdhc_cdns_send_cmd()
615 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS10, SRS10_VAL_READ); in sdhc_cdns_send_cmd()
616 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_VAL_GEN); in sdhc_cdns_send_cmd()
617 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS15, SRS15_VAL_RD_WR); in sdhc_cdns_send_cmd()
624 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS10, SRS10_VAL_READ); in sdhc_cdns_send_cmd()
625 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_VAL_GEN); in sdhc_cdns_send_cmd()
[all …]
/Zephyr-Core-3.6.0/drivers/ethernet/
Deth_cyclonev.c83 sys_set_bits(RSTMGR_PERMODRST_ADDR, Rstmgr_Permodrst_Emac_Set_Msk[instance]); in eth_cyclonev_reset()
180 sys_set_bits(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr), EMAC_DMA_MODE_SWR_SET_MSK); in eth_cyclonev_software_reset()
335 sys_set_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
484 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR( in eth_cyclonev_send()
488 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR( in eth_cyclonev_send()
962 sys_set_bits(EMAC_DMA_INT_EN_ADDR(p->base_addr), interrupt_mask); in eth_cyclonev_probe()
1025 sys_set_bits(EMAC_GMAC_INT_MSK_ADDR(p->base_addr), in eth_cyclonev_probe()
1064 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1066 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1070 sys_set_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_start()
[all …]
/Zephyr-Core-3.6.0/drivers/spi/
Dspi_andes_atcspi200.c67 sys_set_bits(SPI_TIMIN(cfg->base), sclk_div); in spi_config()
78 sys_set_bits(SPI_TFMAT(cfg->base), (data_len << TFMAT_DATA_LEN_OFFSET)); in spi_config()
82 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
88 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
95 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_LSB_MSK); in spi_config()
104 sys_set_bits(SPI_CTRL(cfg->base), TX_FIFO_THRESHOLD << CTRL_TX_THRES_OFFSET); in spi_config()
105 sys_set_bits(SPI_CTRL(cfg->base), RX_FIFO_THRESHOLD << CTRL_RX_THRES_OFFSET); in spi_config()
203 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_enable()
217 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_enable()
622 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_FIFO_RST_MSK); in transceive()
[all …]
/Zephyr-Core-3.6.0/drivers/gpio/
Dgpio_altera_pio.c96 sys_set_bits(addr, BIT(pin)); in gpio_altera_configure()
148 sys_set_bits(addr, mask); in gpio_altera_port_set_bits_raw()
236 sys_set_bits(addr, BIT(pin)); in gpio_altera_pin_interrupt_configure()
/Zephyr-Core-3.6.0/drivers/usb/udc/
Dudc_dwc2_vendor_quirks.h67 sys_set_bits(ggpio_reg, USB_DWC2_GGPIO_STM32_PWRDWN | USB_DWC2_GGPIO_STM32_VBDEN); in pwr_on_stm32f4_fsotg()
Dudc_dwc2.c251 sys_set_bits(reg, epmsk); in dwc2_set_epint()
329 sys_set_bits(diepctl_reg, USB_DWC2_DEPCTL_EPENA | USB_DWC2_DEPCTL_CNAK); in dwc2_tx_fifo_write()
404 sys_set_bits(doepctl_reg, USB_DWC2_DEPCTL_EPENA); in dwc2_prep_rx()
406 sys_set_bits(doepctl_reg, USB_DWC2_DEPCTL_EPENA | USB_DWC2_DEPCTL_CNAK); in dwc2_prep_rx()
660 sys_set_bits((mem_addr_t)&base->gintmsk, USB_DWC2_GINTSTS_RXFLVL); in dwc2_on_bus_reset()
661 sys_set_bits((mem_addr_t)&base->diepmsk, USB_DWC2_DIEPINT_XFERCOMPL); in dwc2_on_bus_reset()
1230 sys_set_bits(dwc2_get_dxepctl_reg(dev, cfg->addr), USB_DWC2_DEPCTL_STALL); in udc_dwc2_ep_set_halt()
1261 sys_set_bits(dcfg_reg, usb_dwc2_set_dcfg_devaddr(addr)); in udc_dwc2_set_address()
1288 sys_set_bits(dctl_reg, usb_dwc2_set_dctl_tstctl(mode)); in udc_dwc2_test_mode()
1339 sys_set_bits(dctl_reg, USB_DWC2_DCTL_SFTDISCON); in udc_dwc2_disable()
[all …]
/Zephyr-Core-3.6.0/include/zephyr/arch/common/
Dsys_bitops.h45 static ALWAYS_INLINE void sys_set_bits(mem_addr_t addr, unsigned int mask) in sys_set_bits() function
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_agilex_ll.c21 #define mmio_setbits_32(addr, mask) sys_set_bits((addr), (mask))
Dclock_stm32_ll_wba.c73 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
116 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_common.c211 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
260 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_h5.c156 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
196 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_u5.c160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
202 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_h7.c373 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr); in stm32_clock_control_on()
421 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
/Zephyr-Core-3.6.0/drivers/flash/
Dflash_andes_qspi.c703 sys_set_bits(QSPI_TIMIN(base), TIMIN_SCLK_DIV_MSK); in qspi_andes_configure()
713 sys_set_bits(QSPI_TFMAT(base), (7 << TFMAT_DATA_LEN_OFFSET)); in qspi_andes_configure()
719 sys_set_bits(QSPI_CTRL(base), TX_FIFO_THRESHOLD); in qspi_andes_configure()
720 sys_set_bits(QSPI_CTRL(base), RX_FIFO_THRESHOLD); in qspi_andes_configure()
Dflash_cadence_qspi_nor_ll.c39 sys_set_bits(cad_params->reg_base + CAD_QSPI_CFG, CAD_QSPI_CFG_BAUDDIV(div)); in cad_qspi_set_baudrate_div()
400 sys_set_bits(cad_params->reg_base + CAD_QSPI_CFG, CAD_QSPI_CFG_ENABLE); in cad_qspi_enable()
Dflash_cadence_nand_ll.c258 sys_set_bits(CNF_MINICTRL(base_address, CMN_SETTINGS), in cdns_nand_set_opr_mode()
/Zephyr-Core-3.6.0/drivers/dai/intel/alh/
Dalh.c87 sys_set_bits(ADSP_DSPALHO_ADDRESS, DSPALHO_ASO_FLAG | DSPALHO_CSO_FLAG); in alh_claim_ownership()