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Searched refs:sys_read32 (Results 1 – 25 of 160) sorted by relevance

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/Zephyr-Core-3.6.0/drivers/watchdog/
Dwdt_dw.h307 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_enable()
327 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_response_mode_set()
345 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_reset_pulse_length_set()
361 uint32_t timeout = sys_read32(base + WDT_TORR); in dw_wdt_timeout_period_set()
376 return FIELD_GET(WDT_TORR_TOP, sys_read32(base + WDT_TORR)); in dw_wdt_timeout_period_get()
388 uint32_t timeout = sys_read32(base + WDT_TORR); in dw_wdt_timeout_period_init_set()
405 uint32_t current_counter_value = sys_read32(base + WDT_CCVR); in dw_wdt_current_counter_value_register_get()
432 return sys_read32(base + WDT_STAT) & 1; in dw_wdt_interrupt_status_register_get()
444 sys_read32(base + WDT_EOI); in dw_wdt_clear_interrupt()
455 return sys_read32(base + WDT_COMP_PARAM_5); in dw_wdt_user_top_max_get()
[all …]
Dwdt_intel_adsp.h94 control = sys_read32(reg_addr); in intel_adsp_wdt_pause()
113 control = sys_read32(reg_addr); in intel_adsp_wdt_resume()
151 return FIELD_GET(DSPCxWDTIPPTR_PTR, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core))); in intel_adsp_wdt_pointer_get()
164 return FIELD_GET(DSPCxWDTIPPTR_VER, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core))); in intel_adsp_wdt_version_get()
/Zephyr-Core-3.6.0/drivers/counter/
Dcounter_ace_v1x_art.c21 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_ionte_set()
31 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_cdmas_set()
41 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_ntk_set()
49 return FIELD_GET(ACE_TSCTRL_NTK_MASK, sys_read32(ACE_TSCTRL)); in counter_ace_v1x_art_ntk_get()
56 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_hhtse_set()
67 hi0 = sys_read32(ACE_ARTCS_HI); in counter_ace_v1x_art_counter_get()
68 lo = sys_read32(ACE_ARTCS_LO); in counter_ace_v1x_art_counter_get()
69 hi1 = sys_read32(ACE_ARTCS_HI); in counter_ace_v1x_art_counter_get()
Dcounter_andes_atcpit100.c78 top = sys_read32(PIT_CH_RELD(dev, ch)) + 1; in get_current_tick()
79 now_cnt = top - sys_read32(PIT_CH_CNTR(dev, ch)); in get_current_tick()
92 ch_enable = sys_read32(PIT_CHEN(dev)); in atcpit100_irq_handler()
93 int_enable = sys_read32(PIT_INTE(dev)); in atcpit100_irq_handler()
94 int_status = sys_read32(PIT_ISTA(dev)); in atcpit100_irq_handler()
164 reg = sys_read32(PIT_CHEN(dev)); in atcpit100_start()
182 reg = sys_read32(PIT_INTE(dev)); in atcpit100_stop()
187 reg = sys_read32(PIT_CHEN(dev)); in atcpit100_stop()
237 top = sys_read32(PIT_CH_RELD(dev, 3)) + 1; in atcpit100_set_alarm()
238 remain_cnt = sys_read32(PIT_CH_CNTR(dev, 3)); in atcpit100_set_alarm()
[all …]
Dcounter_ace_v1x_rtc.c21 hi0 = sys_read32(ACE_RTCWC_HI); in counter_ace_v1x_rtc_get_value()
22 lo = sys_read32(ACE_RTCWC_LO); in counter_ace_v1x_rtc_get_value()
23 hi1 = sys_read32(ACE_RTCWC_HI); in counter_ace_v1x_rtc_get_value()
/Zephyr-Core-3.6.0/soc/arm/aspeed/ast10x0/
Dsoc.c93 jtag_pinmux = sys_read32(base + JTAG_PINMUX_REG); in z_arm_platform_init()
108 if (sys_read32(HW_STRAP2_SCU510) & BIT(11)) { in aspeed_print_abr_wdt_mode()
110 if (sys_read32(HW_STRAP2_SCU510) & BIT(12)) in aspeed_print_abr_wdt_mode()
116 (sys_read32(ASPEED_FMC_WDT2_CTRL) & BIT(4)) ? "Alternate" : "Primary", in aspeed_print_abr_wdt_mode()
117 (sys_read32(HW_STRAP1_SCU500) & BIT(3)) ? 1 : 0); in aspeed_print_abr_wdt_mode()
119 if (sys_read32(HW_STRAP2_SCU510) & GENMASK(15, 13)) { in aspeed_print_abr_wdt_mode()
121 BIT((sys_read32(HW_STRAP2_SCU510) >> 13) & 0x7) / 2); in aspeed_print_abr_wdt_mode()
129 uint32_t rest1 = sys_read32(SYS_RESET_LOG_REG1); in aspeed_print_sysrst_info()
130 uint32_t rest2 = sys_read32(SYS_RESET_LOG_REG2); in aspeed_print_sysrst_info()
/Zephyr-Core-3.6.0/include/zephyr/arch/arm/cortex_a_r/
Dtimer.h56 ctrl = sys_read32(TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_set_compare()
82 return (uint8_t)(sys_read32(TIMER_REG_GET(TIMER_ISR)) & TIMER_ISR_EVENT_FLAG); in arm_arch_timer_get_int_status()
96 ctrl = sys_read32(TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_enable()
110 ctrl = sys_read32(TIMER_REG_GET(TIMER_CTRL)); in arm_arch_timer_set_irq_mask()
134 upper = sys_read32(TIMER_REG_GET(TIMER_CNT_UPPER)); in arm_arch_timer_count()
137 lower = sys_read32(TIMER_REG_GET(TIMER_CNT_LOWER)); in arm_arch_timer_count()
138 upper = sys_read32(TIMER_REG_GET(TIMER_CNT_UPPER)); in arm_arch_timer_count()
/Zephyr-Core-3.6.0/drivers/gpio/
Dgpio_xlnx_ps_bank.c64 dirm_data = sys_read32(GPIO_XLNX_PS_BANK_DIRM_REG); in gpio_xlnx_ps_pin_configure()
65 oen_data = sys_read32(GPIO_XLNX_PS_BANK_OEN_REG); in gpio_xlnx_ps_pin_configure()
86 bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_pin_configure()
132 *value = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_get()
165 bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_set_masked()
193 bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_set_bits()
221 bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_clear_bits()
249 bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG); in gpio_xlnx_ps_bank_toggle_bits()
296 int_type_data = sys_read32(GPIO_XLNX_PS_BANK_INT_TYPE_REG); in gpio_xlnx_ps_bank_pin_irq_configure()
297 int_polarity_data = sys_read32(GPIO_XLNX_PS_BANK_INT_POLARITY_REG); in gpio_xlnx_ps_bank_pin_irq_configure()
[all …]
Dgpio_bcm2711.c85 regval = sys_read32(GPFSEL(data->base, group)); in gpio_bcm2711_pin_configure()
99 regval = sys_read32(GPSET(data->base, group)); in gpio_bcm2711_pin_configure()
103 regval = sys_read32(GPCLR(data->base, group)); in gpio_bcm2711_pin_configure()
114 regval = sys_read32(GPPULL(data->base, group)); in gpio_bcm2711_pin_configure()
133 regval = ((uint64_t)sys_read32(GPLEV(data->base, 0))) | in gpio_bcm2711_port_get_raw()
134 ((uint64_t)sys_read32(GPLEV(data->base, 1)) << 32); in gpio_bcm2711_port_get_raw()
201 regval = ((uint64_t)sys_read32(GPLEV(data->base, 0))) | in gpio_bcm2711_port_toggle_bits()
202 ((uint64_t)sys_read32(GPLEV(data->base, 1)) << 32); in gpio_bcm2711_port_toggle_bits()
230 regval = sys_read32(GPREN(data->base, group)); in gpio_bcm2711_pin_interrupt_configure()
234 regval = sys_read32(GPFEN(data->base, group)); in gpio_bcm2711_pin_interrupt_configure()
[all …]
Dgpio_andes_atcgpio100.c127 port_value = sys_read32(GPIO_DIR(port)); in gpio_atcgpio100_config()
146 port_value = sys_read32(GPIO_DEBE(port)); in gpio_atcgpio100_config()
151 port_value = sys_read32(GPIO_DIR(port)); in gpio_atcgpio100_config()
166 *value = sys_read32(GPIO_DIN(port)); in gpio_atcgpio100_port_get_raw()
179 port_value = sys_read32(GPIO_DOUT(port)); in gpio_atcgpio100_set_masked_raw()
209 port_value = sys_read32(GPIO_DOUT(port)); in gpio_atcgpio100_toggle_bits()
255 port_value = sys_read32(GPIO_INTE(port)); in gpio_atcgpio100_pin_interrupt_configure()
259 port_value = sys_read32(GPIO_ISTA(port)); in gpio_atcgpio100_pin_interrupt_configure()
263 port_value = sys_read32(GPIO_IMD(port, imr_idx)); in gpio_atcgpio100_pin_interrupt_configure()
268 port_value = sys_read32(GPIO_INTE(port)); in gpio_atcgpio100_pin_interrupt_configure()
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/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_control_agilex5_ll.c56 ref_clk = sys_read32(scr_reg); in get_ref_clk()
65 ref_clk = sys_read32(scr_reg); in get_ref_clk()
87 clk_psrc = sys_read32(clock_agilex5_ll.mainpll_addr + psrc_reg); in get_clk_freq()
106 ref_clk = get_ref_clk(sys_read32(pllglob_reg)); in get_clk_freq()
107 mdiv = CLKMGR_PLLM_MDIV(sys_read32(pllm_reg)); in get_clk_freq()
111 pllc_div = CLKMGR_PLLC_DIV(sys_read32(pllc_reg)); in get_clk_freq()
151 mainpll_nocdiv = sys_read32(clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_NOCDIV); in get_uart_clk()
166 sdmmc_ctr = sys_read32(clock_agilex5_ll.ctl_addr + CLKMGR_INTEL_SDMMCCTR); in get_mmc_clk()
/Zephyr-Core-3.6.0/drivers/timer/
Drcar_cmt_timer.c67 reg_val = sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
83 return sys_read32(TIMER_BASE_ADDR + CMCNT1_OFFSET); in sys_clock_cycle_get_32()
112 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
116 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()
135 while (sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET) & CSR_WRITE_FLAG) { in sys_clock_driver_init()
141 if (!sys_read32(TIMER_BASE_ADDR + CMCNT0_OFFSET)) { in sys_clock_driver_init()
146 __ASSERT(sys_read32(TIMER_BASE_ADDR + CMCNT0_OFFSET) == 0, in sys_clock_driver_init()
Dintel_adsp_timer.c66 sys_write32(sys_read32(DSPWCTCS_ADDR) & (~DSP_WCT_CS_TA(COMPARATOR_IDX)), in set_compare()
73 sys_write32(sys_read32(DSPWCTCS_ADDR) | (DSP_WCT_CS_TA(COMPARATOR_IDX)), in set_compare()
88 hi0 = sys_read32(DSPWC_HI_ADDR); in count()
89 lo = sys_read32(DSPWC_LO_ADDR); in count()
90 hi1 = sys_read32(DSPWC_HI_ADDR); in count()
99 counter_lo = sys_read32(DSPWC_LO_ADDR); in count32()
115 sys_write32(sys_read32(DSPWCTCS_ADDR) | DSP_WCT_CS_TT(COMPARATOR_IDX), in compare_isr()
203 sys_write32(sys_read32(DSPWCTCS_ADDR) | ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX), in irq_init()
Dxlnx_psttc_timer.c59 return sys_read32(TIMER_BASE_ADDR + XTTCPS_COUNT_VALUE_OFFSET); in read_count()
83 sys_read32(TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET); in ttc_isr()
174 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
179 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
193 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_IER_OFFSET); in sys_clock_driver_init()
198 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
/Zephyr-Core-3.6.0/drivers/i2c/
Di2c_andes_atciic100.c51 reg = sys_read32(I2C_CMD(dev)); in i2c_atciic100_default_control()
57 reg = sys_read32(I2C_CFG(dev)); in i2c_atciic100_default_control()
78 reg = sys_read32(I2C_SET(dev)); in i2c_atciic100_default_control()
101 reg = sys_read32(I2C_SET(dev)); in i2c_atciic100_configure()
217 reg = sys_read32(I2C_INTE(dev)); in i2c_atciic100_controller_send()
222 reg = sys_read32(I2C_SET(dev)); in i2c_atciic100_controller_send()
232 reg = sys_read32(I2C_CMD(dev)); in i2c_atciic100_controller_send()
246 reg = sys_read32(I2C_CTRL(dev)); in i2c_atciic100_controller_send()
269 reg = sys_read32(I2C_ADDR(dev)); in i2c_atciic100_controller_send()
279 reg = sys_read32(I2C_INTE(dev)); in i2c_atciic100_controller_send()
[all …]
Di2c_xilinx_axi.c72 int_status = sys_read32(config->base + REG_ISR); in i2c_xilinx_axi_target_register()
78 int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_target_register()
119 int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_target_unregister()
142 if (sys_read32(config->base + REG_SR) & SR_SRW) { in i2c_xilinx_axi_target_isr()
159 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
179 sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_target_isr()
183 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
223 uint32_t int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_isr()
224 const uint32_t int_status = sys_read32(config->base + REG_ISR) & int_enable; in i2c_xilinx_axi_isr()
232 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_isr()
[all …]
/Zephyr-Core-3.6.0/samples/drivers/led_xec/src/
Dmain.c41 r = sys_read32(bbled_base); in print_bbled_regs()
43 r = sys_read32(bbled_base + 4U); in print_bbled_regs()
45 r = sys_read32(bbled_base + 8U); in print_bbled_regs()
47 r = sys_read32(bbled_base + 0xcU); in print_bbled_regs()
49 r = sys_read32(bbled_base + 0x10U); in print_bbled_regs()
51 r = sys_read32(bbled_base + 0x14U); in print_bbled_regs()
/Zephyr-Core-3.6.0/drivers/hwinfo/
Dhwinfo_esp32.c19 uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG); in z_impl_hwinfo_get_device_id()
20 uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG); in z_impl_hwinfo_get_device_id()
22 uint32_t rdata1 = sys_read32(EFUSE_BLK0_RDATA1_REG); in z_impl_hwinfo_get_device_id()
23 uint32_t rdata2 = sys_read32(EFUSE_BLK0_RDATA2_REG); in z_impl_hwinfo_get_device_id()
Dhwinfo_cc13xx_cc26xx.c29 sys_read32(CCFG_BASE + CCFG_O_IEEE_BLE_0) == 0xFFFFFFFF || in z_impl_hwinfo_get_device_id()
30 sys_read32(CCFG_BASE + CCFG_O_IEEE_BLE_1) == 0xFFFFFFFF) { in z_impl_hwinfo_get_device_id()
37 sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_0) == 0xFFFFFFFF || in z_impl_hwinfo_get_device_id()
38 sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_1) == 0xFFFFFFFF) { in z_impl_hwinfo_get_device_id()
/Zephyr-Core-3.6.0/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c70 *current_time = sys_read32(regs(dev) + ART_L); in tgpio_intel_get_time()
71 *current_time += ((uint64_t)sys_read32(regs(dev) + ART_H) << UINT32_SIZE); in tgpio_intel_get_time()
94 sys_write32(sys_read32(addr + CTL) & ~CTL_EN, addr + CTL); in tgpio_intel_pin_disable()
169 sys_write32(sys_read32(addr + CTL) | CTL_EN, addr + CTL); in tgpio_intel_config_external_timestamp()
183 *timestamp = sys_read32(regs(dev) + TCV31_0); in tgpio_intel_read_ts_ec()
184 *timestamp += ((uint64_t)sys_read32(regs(dev) + TCV63_32) << UINT32_SIZE); in tgpio_intel_read_ts_ec()
185 *event_count = sys_read32(regs(dev) + ECCV31_0); in tgpio_intel_read_ts_ec()
186 *event_count += ((uint64_t)sys_read32(regs(dev) + ECCV63_32) << UINT32_SIZE); in tgpio_intel_read_ts_ec()
/Zephyr-Core-3.6.0/drivers/serial/
Duart_xlnx_ps.c182 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
206 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
304 reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
346 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_in()
349 *c = (unsigned char)sys_read32(reg_base + XUARTPS_FIFO_OFFSET); in uart_xlnx_ps_poll_in()
377 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_out()
383 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_out()
609 mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_configure()
610 modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET); in uart_xlnx_ps_configure()
817 uint32_t mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_config_get()
[all …]
/Zephyr-Core-3.6.0/drivers/dai/intel/dmic/
Ddmic.c34 #define sys_read64(addr) (((uint64_t)(sys_read32(addr + 4)) << 32) | \
35 sys_read32(addr))
123 sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest); in dai_dmic_update_bits()
135 return sys_read32(dmic->reg_base + reg); in dai_dmic_read()
142 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | in dai_dmic_claim_ownership()
149 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & in dai_dmic_release_ownership()
176 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
178 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, in dai_dmic_set_sync_period()
181 if (!WAIT_FOR((sys_read32(base + DMICSYNC_OFFSET) & DMICSYNC_SYNCPU) == 0, 1000, in dai_dmic_set_sync_period()
186 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, in dai_dmic_set_sync_period()
[all …]
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/
Dtimestamp.c42 tsctrl_temp = sys_read32(TSCTRL_ADDR); in intel_adsp_get_timestamp()
72 tsctrl_temp = sys_read32(TSCTRL_ADDR); in intel_adsp_get_timestamp()
82 timestamp->iscs = sys_read32(ISCS_ADDR); in intel_adsp_get_timestamp()
86 timestamp->lwccs = sys_read32(LWCCS_ADDR); in intel_adsp_get_timestamp()
/Zephyr-Core-3.6.0/drivers/interrupt_controller/
Dintc_gicv3.c69 while (sys_read32(base) & rwp_mask) { in gic_wait_rwp()
153 val = sys_read32(ICFGR(base, idx)); in arm_gic_irq_set_priority()
214 val = sys_read32(ISENABLER(GET_DIST_BASE(intid), idx)); in arm_gic_irq_is_enabled()
225 val = sys_read32(ISPENDR(GET_DIST_BASE(intid), idx)); in arm_gic_irq_is_pending()
300 if (!(sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))) { in gicv3_rdist_enable()
304 if (GICR_IIDR_PRODUCT_ID_GET(sys_read32(rdist + GICR_IIDR)) >= 0x2) { in gicv3_rdist_enable()
305 if (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) { in gicv3_rdist_enable()
308 while (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) { in gicv3_rdist_enable()
315 while (sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)) { in gicv3_rdist_enable()
327 unsigned int lpi_id_bits = MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)), in gicv3_rdist_setup_lpis()
[all …]
Dintc_vim.c27 vec_addr = sys_read32(VIM_IRQVEC); in z_vim_irq_get_active()
30 actirq = sys_read32(VIM_ACTIRQ); in z_vim_irq_get_active()
59 uint32_t num_of_irqs = sys_read32(VIM_INFO_INTERRUPTS_MASK); in z_vim_irq_init()
80 regval = sys_read32(VIM_INTTYPE(irq_group_num)); in z_vim_irq_priority_set()
133 regval = sys_read32(VIM_INTR_EN_SET(irq_group_num)); in z_vim_irq_is_enabled()

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