1 /*
2 * Copyright (C) 2023 BeagleBoard.org Foundation
3 * Copyright (C) 2023 S Prashanth
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT ti_davinci_gpio
9
10 #include <errno.h>
11
12 #include <zephyr/arch/common/sys_bitops.h>
13 #include <zephyr/device.h>
14 #include <zephyr/devicetree.h>
15 #include <zephyr/drivers/gpio.h>
16 #include <zephyr/drivers/gpio/gpio_utils.h>
17 #include <zephyr/init.h>
18 #include <zephyr/kernel.h>
19 #include <zephyr/sys/sys_io.h>
20 #include <zephyr/logging/log.h>
21 #include <zephyr/drivers/pinctrl.h>
22
23 LOG_MODULE_REGISTER(gpio_davinci, CONFIG_GPIO_LOG_LEVEL);
24
25 /* Helper Macros for GPIO */
26 #define DEV_CFG(dev) \
27 ((const struct gpio_davinci_config *)((dev)->config))
28 #define DEV_DATA(dev) ((struct gpio_davinci_data *)(dev)->data)
29 #define DEV_GPIO_CFG_BASE(dev) \
30 ((struct gpio_davinci_regs *)DEVICE_MMIO_NAMED_GET(dev, port_base))
31
32 #define GPIO_DAVINCI_DIR_RESET_VAL (0xFFFFFFFF)
33
34 struct gpio_davinci_regs {
35 uint32_t dir;
36 uint32_t out_data;
37 uint32_t set_data;
38 uint32_t clr_data;
39 uint32_t in_data;
40 uint32_t set_ris_trig;
41 uint32_t clr_ris_trig;
42 uint32_t set_fal_trig;
43 uint32_t clr_fal_trig;
44 uint32_t intstat;
45 };
46
47 struct gpio_davinci_data {
48 struct gpio_driver_data common;
49
50 DEVICE_MMIO_NAMED_RAM(port_base);
51
52 sys_slist_t cb;
53 };
54
55 struct gpio_davinci_config {
56 void (*bank_config)(const struct device *dev);
57 struct gpio_driver_config common;
58
59 DEVICE_MMIO_NAMED_ROM(port_base);
60
61 uint32_t port_num;
62 const struct pinctrl_dev_config *pcfg;
63 };
64
gpio_davinci_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)65 static int gpio_davinci_configure(const struct device *dev, gpio_pin_t pin,
66 gpio_flags_t flags)
67 {
68 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
69
70 if ((flags & GPIO_SINGLE_ENDED) != 0) {
71 return -ENOTSUP;
72 }
73
74 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
75 return -ENOTSUP;
76 }
77
78 if ((flags & GPIO_OUTPUT) != 0) {
79 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
80 regs->set_data = BIT(pin);
81 } else {
82 regs->clr_data = BIT(pin);
83 }
84 regs->dir &= ~(BIT(pin));
85 } else {
86 regs->dir |= BIT(pin);
87 }
88
89 return 0;
90 }
91
gpio_davinci_port_get_raw(const struct device * dev,gpio_port_value_t * value)92 static int gpio_davinci_port_get_raw(const struct device *dev,
93 gpio_port_value_t *value)
94 {
95 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
96
97 *value = regs->in_data;
98
99 return 0;
100 }
101
gpio_davinci_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)102 static int gpio_davinci_port_set_masked_raw(const struct device *dev,
103 gpio_port_pins_t mask, gpio_port_value_t value)
104 {
105 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
106
107 regs->out_data = (regs->out_data & (~mask)) | (mask & value);
108
109 return 0;
110 }
111
gpio_davinci_port_set_bits_raw(const struct device * dev,gpio_port_pins_t mask)112 static int gpio_davinci_port_set_bits_raw(const struct device *dev,
113 gpio_port_pins_t mask)
114 {
115 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
116
117 regs->set_data |= mask;
118
119 return 0;
120 }
121
gpio_davinci_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t mask)122 static int gpio_davinci_port_clear_bits_raw(const struct device *dev,
123 gpio_port_pins_t mask)
124 {
125 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
126
127 regs->clr_data |= mask;
128
129 return 0;
130 }
131
gpio_davinci_port_toggle_bits(const struct device * dev,gpio_port_pins_t mask)132 static int gpio_davinci_port_toggle_bits(const struct device *dev,
133 gpio_port_pins_t mask)
134 {
135 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
136
137 regs->out_data ^= mask;
138
139 return 0;
140 }
141
142 static const struct gpio_driver_api gpio_davinci_driver_api = {
143 .pin_configure = gpio_davinci_configure,
144 .port_get_raw = gpio_davinci_port_get_raw,
145 .port_set_masked_raw = gpio_davinci_port_set_masked_raw,
146 .port_set_bits_raw = gpio_davinci_port_set_bits_raw,
147 .port_clear_bits_raw = gpio_davinci_port_clear_bits_raw,
148 .port_toggle_bits = gpio_davinci_port_toggle_bits
149 };
150
gpio_davinci_init(const struct device * dev)151 static int gpio_davinci_init(const struct device *dev)
152 {
153 const struct gpio_davinci_config *config = DEV_CFG(dev);
154 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev);
155 int ret;
156
157 DEVICE_MMIO_NAMED_MAP(dev, port_base, K_MEM_CACHE_NONE);
158
159 regs->dir = GPIO_DAVINCI_DIR_RESET_VAL;
160
161 config->bank_config(dev);
162
163 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
164 if (ret < 0) {
165 LOG_ERR("failed to apply pinctrl");
166 return ret;
167 }
168 return 0;
169 }
170
171 #define GPIO_DAVINCI_INIT_FUNC(n) \
172 static void gpio_davinci_bank_##n##_config(const struct device *dev) \
173 { \
174 volatile struct gpio_davinci_regs *regs = DEV_GPIO_CFG_BASE(dev); \
175 ARG_UNUSED(regs); \
176 }
177
178 #define GPIO_DAVINCI_INIT(n) \
179 PINCTRL_DT_INST_DEFINE(n); \
180 GPIO_DAVINCI_INIT_FUNC(n); \
181 static const struct gpio_davinci_config gpio_davinci_##n##_config = { \
182 .bank_config = gpio_davinci_bank_##n##_config, \
183 .common = { \
184 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
185 }, \
186 DEVICE_MMIO_NAMED_ROM_INIT(port_base, DT_DRV_INST(n)), \
187 .port_num = n, \
188 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
189 }; \
190 \
191 static struct gpio_davinci_data gpio_davinci_##n##_data; \
192 \
193 DEVICE_DT_INST_DEFINE(n, \
194 &gpio_davinci_init, \
195 NULL, \
196 &gpio_davinci_##n##_data, \
197 &gpio_davinci_##n##_config, \
198 PRE_KERNEL_2, \
199 CONFIG_GPIO_INIT_PRIORITY, \
200 &gpio_davinci_driver_api);
201
202 DT_INST_FOREACH_STATUS_OKAY(GPIO_DAVINCI_INIT)
203
