1 /* disc_access_sdhc.h - header SDHC*/
2
3 /*
4 * Copyright (c) 2019 NXP
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8 #ifndef ZEPHYR_INCLUDE_DISK_DRIVER_SDMMC_H_
9 #define ZEPHYR_INCLUDE_DISK_DRIVER_SDMMC_H_
10
11 #include <zephyr/drivers/spi.h>
12
13 #define SDMMC_CLOCK_400KHZ (400000U)
14 #define SD_CLOCK_25MHZ (25000000U)
15 #define SD_CLOCK_50MHZ (50000000U)
16 #define SD_CLOCK_100MHZ (100000000U)
17 #define SD_CLOCK_208MHZ (208000000U)
18 #define MMC_CLOCK_26MHZ (26000000U)
19 #define MMC_CLOCK_52MHZ (52000000U)
20 #define MMC_CLOCK_DDR52 (52000000U)
21 #define MMC_CLOCK_HS200 (200000000U)
22 #define MMC_CLOCK_HS400 (400000000U)
23
24 /* Command IDs */
25 #define SDHC_GO_IDLE_STATE 0
26 #define SDHC_ALL_SEND_CID 2
27 #define SDHC_SEND_RELATIVE_ADDR 3
28 #define SDHC_SWITCH 6
29 #define SDHC_SELECT_CARD 7
30 #define SDHC_SEND_IF_COND 8
31 #define SDHC_SEND_CSD 9
32 #define SDHC_SEND_CID 10
33 #define SDHC_VOL_SWITCH 11
34 #define SDHC_STOP_TRANSMISSION 12
35 #define SDHC_SEND_STATUS 13
36 #define SDHC_GO_INACTIVE_STATE 15
37 #define SDHC_SET_BLOCK_SIZE 16
38 #define SDHC_READ_SINGLE_BLOCK 17
39 #define SDHC_READ_MULTIPLE_BLOCK 18
40 #define SDHC_SEND_TUNING_BLOCK 19
41 #define SDHC_SET_BLOCK_COUNT 23
42 #define SDHC_WRITE_BLOCK 24
43 #define SDHC_WRITE_MULTIPLE_BLOCK 25
44 #define SDHC_ERASE_BLOCK_START 32
45 #define SDHC_ERASE_BLOCK_END 33
46 #define SDHC_ERASE_BLOCK_OPERATION 38
47 #define SDHC_APP_CMD 55
48 #define SDHC_READ_OCR 58
49 #define SDHC_CRC_ON_OFF 59
50
51 enum sdhc_app_ext_cmd {
52 SDHC_APP_SET_BUS_WIDTH = 6,
53 SDHC_APP_SEND_STATUS = 13,
54 SDHC_APP_SEND_NUM_WRITTEN_BLK = 22,
55 SDHC_APP_SET_WRITE_BLK_ERASE_CNT = 23,
56 SDHC_APP_SEND_OP_COND = 41,
57 SDHC_APP_CLEAR_CARD_DETECT = 42,
58 SDHC_APP_SEND_SCR = 51
59 };
60
61 #define SDHC_SEND_OP_COND SDHC_APP_SEND_OP_COND
62
63 /* R1 response status */
64 #define SDHC_R1_IDLE 0x01
65 #define SDHC_R1_ERASE_RESET 0x02
66 #define SDHC_R1_ILLEGAL_COMMAND 0x04
67 #define SDHC_R1_COM_CRC 0x08
68 #define SDHC_R1_ERASE_SEQ 0x10
69 #define SDHC_R1_ADDRESS 0x20
70 #define SDHC_R1_PARAMETER 0x40
71
72 #define SDHC_CMD_SIZE 6
73 #define SDHC_CMD_BODY_SIZE (SDHC_CMD_SIZE - 1)
74 #define SDHC_CRC16_SIZE 2
75
76 /* Command flags */
77 #define SDHC_START 0x80
78 #define SDHC_TX 0x40
79
80 /* Fields in various card registers */
81 #define SDHC_HCS (1 << 30)
82 #define SDHC_CCS (1 << 30)
83 #define SDHC_BUSY (1 << 31)
84 #define SDHC_VHS_MASK (0x0F << 8)
85 #define SDHC_VHS_3V3 (1 << 8)
86 #define SDHC_CHECK 0xAA
87 #define SDHC_CSD_SIZE 16
88 #define SDHC_CSD_V1 0
89 #define SDHC_CSD_V2 1
90
91 /* Data block tokens */
92 #define SDHC_TOKEN_SINGLE 0xFE
93 #define SDHC_TOKEN_MULTI_WRITE 0xFC
94 #define SDHC_TOKEN_STOP_TRAN 0xFD
95
96 /* Data block responses */
97 #define SDHC_RESPONSE_ACCEPTED 0x05
98 #define SDHC_RESPONSE_CRC_ERR 0x0B
99 #define SDHC_RESPONSE_WRITE_ERR 0x0E
100
101 #define SDHC_MIN_TRIES 20
102 #define SDHC_RETRY_DELAY 20
103 /* Time to wait for the card to initialise */
104 #define SDHC_INIT_TIMEOUT 5000
105 /* Time to wait for the card to respond or come ready */
106 #define SDHC_READY_TIMEOUT 500
107
108 enum sdhc_rsp_type {
109 SDHC_RSP_TYPE_NONE = 0U,
110 SDHC_RSP_TYPE_R1 = 1U,
111 SDHC_RSP_TYPE_R1b = 2U,
112 SDHC_RSP_TYPE_R2 = 3U,
113 SDHC_RSP_TYPE_R3 = 4U,
114 SDHC_RSP_TYPE_R4 = 5U,
115 SDHC_RSP_TYPE_R5 = 6U,
116 SDHC_RSP_TYPE_R5b = 7U,
117 SDHC_RSP_TYPE_R6 = 8U,
118 SDHC_RSP_TYPE_R7 = 9U,
119 };
120
121 enum sdhc_bus_width {
122 SDHC_BUS_WIDTH1BIT = 0U,
123 SDHC_BUS_WIDTH4BIT = 1U,
124 };
125
126 enum sdhc_flag {
127 SDHC_HIGH_CAPACITY_FLAG = (1U << 1U),
128 SDHC_4BITS_WIDTH = (1U << 2U),
129 SDHC_SDHC_FLAG = (1U << 3U),
130 SDHC_SDXC_FLAG = (1U << 4U),
131 SDHC_1800MV_FLAG = (1U << 5U),
132 SDHC_CMD23_FLAG = (1U << 6U),
133 SDHC_SPEED_CLASS_CONTROL_FLAG = (1U << 7U),
134 };
135
136 enum sdhc_r1_error_flag {
137 SDHC_R1OUTOF_RANGE_ERR = (1U << 31U),
138 SDHC_R1ADDRESS_ERR = (1U << 30U),
139 SDHC_R1BLK_LEN_ERR = (1U << 29U),
140 SDHC_R1ERASE_SEQ_ERR = (1U << 28U),
141 SDHC_R1ERASE_PARAMETER_ERR = (1U << 27U),
142 SDHC_R1WRITE_PROTECTION_ERR = (1U << 26U),
143 SDHC_R1CARD_LOCKED_ERR = (1U << 25U),
144 SDHC_R1LOCK_UNLOCK_ERR = (1U << 24U),
145 SDHC_R1CMD_CRC_ERR = (1U << 23U),
146 SDHC_R1ILLEGAL_CMD_ERR = (1U << 22U),
147 SDHC_R1ECC_ERR = (1U << 21U),
148 SDHC_R1CARD_CONTROL_ERR = (1U << 20U),
149 SDHC_R1ERR = (1U << 19U),
150 SDHC_R1CID_CSD_OVERWRITE_ERR = (1U << 16U),
151 SDHC_R1WRITE_PROTECTION_ERASE_SKIP = (1U << 15U),
152 SDHC_R1CARD_ECC_DISABLED = (1U << 14U),
153 SDHC_R1ERASE_RESET = (1U << 13U),
154 SDHC_R1READY_FOR_DATA = (1U << 8U),
155 SDHC_R1SWITCH_ERR = (1U << 7U),
156 SDHC_R1APP_CMD = (1U << 5U),
157 SDHC_R1AUTH_SEQ_ERR = (1U << 3U),
158
159 SDHC_R1ERR_All_FLAG =
160 (SDHC_R1OUTOF_RANGE_ERR |
161 SDHC_R1ADDRESS_ERR |
162 SDHC_R1BLK_LEN_ERR |
163 SDHC_R1ERASE_SEQ_ERR |
164 SDHC_R1ERASE_PARAMETER_ERR |
165 SDHC_R1WRITE_PROTECTION_ERR |
166 SDHC_R1CARD_LOCKED_ERR |
167 SDHC_R1LOCK_UNLOCK_ERR |
168 SDHC_R1CMD_CRC_ERR |
169 SDHC_R1ILLEGAL_CMD_ERR |
170 SDHC_R1ECC_ERR |
171 SDHC_R1CARD_CONTROL_ERR |
172 SDHC_R1ERR |
173 SDHC_R1CID_CSD_OVERWRITE_ERR |
174 SDHC_R1AUTH_SEQ_ERR),
175
176 SDHC_R1ERR_NONE = 0,
177 };
178
179 #define SD_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U)
180
181 enum sd_r1_current_state {
182 SDMMC_R1_IDLE = 0U,
183 SDMMC_R1_READY = 1U,
184 SDMMC_R1_IDENTIFY = 2U,
185 SDMMC_R1_STANDBY = 3U,
186 SDMMC_R1_TRANSFER = 4U,
187 SDMMC_R1_SEND_DATA = 5U,
188 SDMMC_R1_RECIVE_DATA = 6U,
189 SDMMC_R1_PROGRAM = 7U,
190 SDMMC_R1_DISCONNECT = 8U,
191 };
192
193 enum sd_ocr_flag {
194 SD_OCR_PWR_BUSY_FLAG = (1U << 31U),
195 /*!< Power up busy status */
196 SD_OCR_HOST_CAP_FLAG = (1U << 30U),
197 /*!< Card capacity status */
198 SD_OCR_CARD_CAP_FLAG = SD_OCR_HOST_CAP_FLAG,
199 /*!< Card capacity status */
200 SD_OCR_SWITCH_18_REQ_FLAG = (1U << 24U),
201 /*!< Switch to 1.8V request */
202 SD_OCR_SWITCH_18_ACCEPT_FLAG = SD_OCR_SWITCH_18_REQ_FLAG,
203 /*!< Switch to 1.8V accepted */
204 SD_OCR_VDD27_28FLAG = (1U << 15U),
205 /*!< VDD 2.7-2.8 */
206 SD_OCR_VDD28_29FLAG = (1U << 16U),
207 /*!< VDD 2.8-2.9 */
208 SD_OCR_VDD29_30FLAG = (1U << 17U),
209 /*!< VDD 2.9-3.0 */
210 SD_OCR_VDD30_31FLAG = (1U << 18U),
211 /*!< VDD 2.9-3.0 */
212 SD_OCR_VDD31_32FLAG = (1U << 19U),
213 /*!< VDD 3.0-3.1 */
214 SD_OCR_VDD32_33FLAG = (1U << 20U),
215 /*!< VDD 3.1-3.2 */
216 SD_OCR_VDD33_34FLAG = (1U << 21U),
217 /*!< VDD 3.2-3.3 */
218 SD_OCR_VDD34_35FLAG = (1U << 22U),
219 /*!< VDD 3.3-3.4 */
220 SD_OCR_VDD35_36FLAG = (1U << 23U),
221 /*!< VDD 3.4-3.5 */
222 };
223
224 #define SD_PRODUCT_NAME_BYTES (5U)
225
226 struct sd_cid {
227 uint8_t manufacturer;
228 /*!< Manufacturer ID [127:120] */
229 uint16_t application;
230 /*!< OEM/Application ID [119:104] */
231 uint8_t name[SD_PRODUCT_NAME_BYTES];
232 /*!< Product name [103:64] */
233 uint8_t version;
234 /*!< Product revision [63:56] */
235 uint32_t ser_num;
236 /*!< Product serial number [55:24] */
237 uint16_t date;
238 /*!< Manufacturing date [19:8] */
239 };
240
241 struct sd_csd {
242 uint8_t csd_structure;
243 /*!< CSD structure [127:126] */
244 uint8_t read_time1;
245 /*!< Data read access-time-1 [119:112] */
246 uint8_t read_time2;
247 /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */
248 uint8_t xfer_rate;
249 /*!< Maximum data transfer rate [103:96] */
250 uint16_t cmd_class;
251 /*!< Card command classes [95:84] */
252 uint8_t read_blk_len;
253 /*!< Maximum read data block length [83:80] */
254 uint16_t flags;
255 /*!< Flags in _sd_csd_flag */
256 uint32_t device_size;
257 /*!< Device size [73:62] */
258 uint8_t read_current_min;
259 /*!< Maximum read current at VDD min [61:59] */
260 uint8_t read_current_max;
261 /*!< Maximum read current at VDD max [58:56] */
262 uint8_t write_current_min;
263 /*!< Maximum write current at VDD min [55:53] */
264 uint8_t write_current_max;
265 /*!< Maximum write current at VDD max [52:50] */
266 uint8_t dev_size_mul;
267 /*!< Device size multiplier [49:47] */
268
269 uint8_t erase_size;
270 /*!< Erase sector size [45:39] */
271 uint8_t write_prtect_size;
272 /*!< Write protect group size [38:32] */
273 uint8_t write_speed_factor;
274 /*!< Write speed factor [28:26] */
275 uint8_t write_blk_len;
276 /*!< Maximum write data block length [25:22] */
277 uint8_t file_fmt;
278 /*!< File format [11:10] */
279 };
280
281 struct sd_scr {
282 uint8_t scr_structure;
283 /*!< SCR Structure [63:60] */
284 uint8_t sd_spec;
285 /*!< SD memory card specification version [59:56] */
286 uint16_t flags;
287 /*!< SCR flags in _sd_scr_flag */
288 uint8_t sd_sec;
289 /*!< Security specification supported [54:52] */
290 uint8_t sd_width;
291 /*!< Data bus widths supported [51:48] */
292 uint8_t sd_ext_sec;
293 /*!< Extended security support [46:43] */
294 uint8_t cmd_support;
295 /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/
296 uint32_t rsvd;
297 /*!< reserved for manufacturer usage [31:0] */
298 };
299
300 enum sd_timing_mode {
301 SD_TIMING_SDR12_DFT_MODE = 0U,
302 /*!< Identification mode & SDR12 */
303 SD_TIMING_SDR25_HIGH_SPEED_MODE = 1U,
304 /*!< High speed mode & SDR25 */
305 SD_TIMING_SDR50_MODE = 2U,
306 /*!< SDR50 mode*/
307 SD_TIMING_SDR104_MODE = 3U,
308 /*!< SDR104 mode */
309 SD_TIMING_DDR50_MODE = 4U,
310 /*!< DDR50 mode */
311 };
312
313 /*! @brief SD card current limit */
314 enum sd_max_current {
315 SD_MAX_CURRENT_200MA = 0U,
316 /*!< default current limit */
317 SD_MAX_CURRENT_400MA = 1U,
318 /*!< current limit to 400MA */
319 SD_MAX_CURRENT_600MA = 2U,
320 /*!< current limit to 600MA */
321 SD_MAX_CURRENT_800MA = 3U,
322 /*!< current limit to 800MA */
323 };
324
325 enum sd_voltage {
326 SD_VOL_NONE = 0U,
327 /*!< indicate current voltage setting is not set by user*/
328 SD_VOL_3_3_V = 1U,
329 /*!< card operation voltage around 3.3v */
330 SD_VOL_3_0_V = 2U,
331 /*!< card operation voltage around 3.0v */
332 SD_VOL_1_8_V = 3U,
333 /*!< card operation voltage around 1.8v */
334 };
335
336 #define SDMMC_DEFAULT_BLOCK_SIZE (512U)
337
338 struct sd_data_op {
339 uint32_t start_block;
340 uint32_t block_size;
341 uint32_t block_count;
342 uint32_t *buf;
343 };
344
345 enum sd_switch_arg {
346 SD_SWITCH_CHECK = 0U,
347 /*!< SD switch mode 0: check function */
348 SD_SWITCH_SET = 1U,
349 /*!< SD switch mode 1: set function */
350 };
351
352 enum sd_group_num {
353 SD_GRP_TIMING_MODE = 0U,
354 /*!< access mode group*/
355 SD_GRP_CMD_SYS_MODE = 1U,
356 /*!< command system group*/
357 SD_GRP_DRIVER_STRENGTH_MODE = 2U,
358 /*!< driver strength group*/
359 SD_GRP_CURRENT_LIMIT_MODE = 3U,
360 /*!< current limit group*/
361 };
362
363 enum sd_driver_strength {
364 SD_DRV_STRENGTH_TYPEB = 0U,
365 /*!< default driver strength*/
366 SD_DRV_STRENGTH_TYPEA = 1U,
367 /*!< driver strength TYPE A */
368 SD_DRV_STRENGTH_TYPEC = 2U,
369 /*!< driver strength TYPE C */
370 SD_DRV_STRENGTH_TYPED = 3U,
371 /*!< driver strength TYPE D */
372 };
373
374 enum sd_csd_flag {
375 SD_CSD_READ_BLK_PARTIAL_FLAG = (1U << 0U),
376 /*!< Partial blocks for read allowed [79:79] */
377 SD_CSD_WRITE_BLK_MISALIGN_FLAG = (1U << 1U),
378 /*!< Write block misalignment [78:78] */
379 SD_CSD_READ_BLK_MISALIGN_FLAG = (1U << 2U),
380 /*!< Read block misalignment [77:77] */
381 SD_CSD_DSR_IMPLEMENTED_FLAG = (1U << 3U),
382 /*!< DSR implemented [76:76] */
383 SD_CSD_ERASE_BLK_EN_FLAG = (1U << 4U),
384 /*!< Erase single block enabled [46:46] */
385 SD_CSD_WRITE_PROTECT_GRP_EN_FLAG = (1U << 5U),
386 /*!< Write protect group enabled [31:31] */
387 SD_CSD_WRITE_BLK_PARTIAL_FLAG = (1U << 6U),
388 /*!< Partial blocks for write allowed [21:21] */
389 SD_CSD_FILE_FMT_GRP_FLAG = (1U << 7U),
390 /*!< File format group [15:15] */
391 SD_CSD_COPY_FLAG = (1U << 8U),
392 /*!< Copy flag [14:14] */
393 SD_CSD_PERMANENT_WRITE_PROTECT_FLAG = (1U << 9U),
394 /*!< Permanent write protection [13:13] */
395 SD_CSD_TMP_WRITE_PROTECT_FLAG = (1U << 10U),
396 /*!< Temporary write protection [12:12] */
397 };
398
399 enum sd_scr_flag {
400 SD_SCR_DATA_STATUS_AFTER_ERASE = (1U << 0U),
401 /*!< Data status after erases [55:55] */
402 SD_SCR_SPEC3 = (1U << 1U),
403 /*!< Specification version 3.00 or higher [47:47]*/
404 };
405
406 enum sd_spec_version {
407 SD_SPEC_VER1_0 = (1U << 0U),
408 /*!< SD card version 1.0-1.01 */
409 SD_SPEC_VER1_1 = (1U << 1U),
410 /*!< SD card version 1.10 */
411 SD_SPEC_VER2_0 = (1U << 2U),
412 /*!< SD card version 2.00 */
413 SD_SPEC_VER3_0 = (1U << 3U),
414 /*!< SD card version 3.0 */
415 };
416
417 enum sd_command_class {
418 SD_CMD_CLASS_BASIC = (1U << 0U),
419 /*!< Card command class 0 */
420 SD_CMD_CLASS_BLOCK_READ = (1U << 2U),
421 /*!< Card command class 2 */
422 SD_CMD_CLASS_BLOCK_WRITE = (1U << 4U),
423 /*!< Card command class 4 */
424 SD_CMD_CLASS_ERASE = (1U << 5U),
425 /*!< Card command class 5 */
426 SD_CMD_CLASS_WRITE_PROTECT = (1U << 6U),
427 /*!< Card command class 6 */
428 SD_CMD_CLASS_LOCKCARD = (1U << 7U),
429 /*!< Card command class 7 */
430 SD_CMD_CLASS_APP_SPECIFIC = (1U << 8U),
431 /*!< Card command class 8 */
432 SD_CMD_CLASS_IO_MODE = (1U << 9U),
433 /*!< Card command class 9 */
434 SD_CMD_CLASS_SWITCH = (1U << 10U),
435 /*!< Card command class 10 */
436 };
437
438 struct sdhc_retry {
439 uint32_t end;
440 int16_t tries;
441 uint16_t sleep;
442 };
443
444 struct sdhc_flag_map {
445 uint8_t mask;
446 uint8_t err;
447 };
448
449 /* The SD protocol requires sending ones while reading but Zephyr
450 * defaults to writing zeros.
451 */
452 static const uint8_t sdhc_ones[] = {
453 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
454 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
455 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
456 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
457 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
458 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
459 };
460
461 BUILD_ASSERT(sizeof(sdhc_ones) % SDHC_CSD_SIZE == 0);
462 BUILD_ASSERT(SDMMC_DEFAULT_BLOCK_SIZE % sizeof(sdhc_ones) == 0);
463
464 /* Maps R1 response flags to error codes */
465 static const struct sdhc_flag_map sdhc_r1_flags[] = {
466 {SDHC_R1_PARAMETER, EFAULT}, {SDHC_R1_ADDRESS, EFAULT},
467 {SDHC_R1_ILLEGAL_COMMAND, EINVAL}, {SDHC_R1_COM_CRC, EILSEQ},
468 {SDHC_R1_ERASE_SEQ, EIO}, {SDHC_R1_ERASE_RESET, EIO},
469 {SDHC_R1_IDLE, ECONNRESET}, {0, 0},
470 };
471
472 /* Maps disk status flags to error codes */
473 static const struct sdhc_flag_map sdhc_disk_status_flags[] = {
474 {DISK_STATUS_UNINIT, ENODEV},
475 {DISK_STATUS_NOMEDIA, ENOENT},
476 {DISK_STATUS_WR_PROTECT, EROFS},
477 {0, 0},
478 };
479
480 /* Maps data block flags to error codes */
481 static const struct sdhc_flag_map sdhc_data_response_flags[] = {
482 {SDHC_RESPONSE_WRITE_ERR, EIO},
483 {SDHC_RESPONSE_CRC_ERR, EILSEQ},
484 {SDHC_RESPONSE_ACCEPTED, 0},
485 /* Unrecognised value */
486 {0, EPROTO},
487 };
488
489 /* Returns true if an error code is retryable at the disk layer */
sdhc_is_retryable(int err)490 static inline bool sdhc_is_retryable(int err)
491 {
492 switch (err) {
493 case 0:
494 return false;
495 case -EILSEQ:
496 case -EIO:
497 case -ETIMEDOUT:
498 return true;
499 default:
500 return false;
501 }
502 }
503
504 /* Maps a flag based error code into a Zephyr errno */
sdhc_map_flags(const struct sdhc_flag_map * map,int flags)505 static inline int sdhc_map_flags(const struct sdhc_flag_map *map, int flags)
506 {
507 if (flags < 0) {
508 return flags;
509 }
510
511 for (; map->mask != 0U; map++) {
512 if ((flags & map->mask) == map->mask) {
513 return -map->err;
514 }
515 }
516
517 return -map->err;
518 }
519
520 /* Converts disk status into an error code */
sdhc_map_disk_status(int status)521 static inline int sdhc_map_disk_status(int status)
522 {
523 return sdhc_map_flags(sdhc_disk_status_flags, status);
524 }
525
526 /* Converts the R1 response flags into an error code */
sdhc_map_r1_status(int status)527 static inline int sdhc_map_r1_status(int status)
528 {
529 return sdhc_map_flags(sdhc_r1_flags, status);
530 }
531
532 /* Converts an early stage idle mode R1 code into an error code */
sdhc_map_r1_idle_status(int status)533 static inline int sdhc_map_r1_idle_status(int status)
534 {
535 if (status < 0) {
536 return status;
537 }
538
539 if (status == SDHC_R1_IDLE) {
540 return 0;
541 }
542
543 return sdhc_map_r1_status(status);
544 }
545
546 /* Converts the data block response flags into an error code */
sdhc_map_data_status(int status)547 static inline int sdhc_map_data_status(int status)
548 {
549 return sdhc_map_flags(sdhc_data_response_flags, status);
550 }
551
552 /* Initialises a retry helper */
sdhc_retry_init(struct sdhc_retry * retry,uint32_t timeout,uint16_t sleep)553 static inline void sdhc_retry_init(struct sdhc_retry *retry, uint32_t timeout,
554 uint16_t sleep)
555 {
556 retry->end = k_uptime_get_32() + timeout;
557 retry->tries = 0;
558 retry->sleep = sleep;
559 }
560
561 /* Called at the end of a retry loop. Returns if the minimum try
562 * count and timeout has passed. Delays/yields on retry.
563 */
sdhc_retry_ok(struct sdhc_retry * retry)564 static inline bool sdhc_retry_ok(struct sdhc_retry *retry)
565 {
566 int32_t remain = retry->end - k_uptime_get_32();
567
568 if (retry->tries < SDHC_MIN_TRIES) {
569 retry->tries++;
570 if (retry->sleep != 0U) {
571 k_msleep(retry->sleep);
572 }
573
574 return true;
575 }
576
577 if (remain >= 0) {
578 if (retry->sleep > 0) {
579 k_msleep(retry->sleep);
580 } else {
581 k_yield();
582 }
583
584 return true;
585 }
586
587 return false;
588 }
589
sdhc_decode_csd(struct sd_csd * csd,uint32_t * raw_csd,uint32_t * blk_cout,uint32_t * blk_size)590 static inline void sdhc_decode_csd(struct sd_csd *csd,
591 uint32_t *raw_csd, uint32_t *blk_cout, uint32_t *blk_size)
592 {
593 uint32_t tmp_blk_cout, tmp_blk_size;
594
595 csd->csd_structure = (uint8_t)((raw_csd[3U] &
596 0xC0000000U) >> 30U);
597 csd->read_time1 = (uint8_t)((raw_csd[3U] &
598 0xFF0000U) >> 16U);
599 csd->read_time2 = (uint8_t)((raw_csd[3U] &
600 0xFF00U) >> 8U);
601 csd->xfer_rate = (uint8_t)(raw_csd[3U] &
602 0xFFU);
603 csd->cmd_class = (uint16_t)((raw_csd[2U] &
604 0xFFF00000U) >> 20U);
605 csd->read_blk_len = (uint8_t)((raw_csd[2U] &
606 0xF0000U) >> 16U);
607 if (raw_csd[2U] & 0x8000U)
608 csd->flags |= SD_CSD_READ_BLK_PARTIAL_FLAG;
609 if (raw_csd[2U] & 0x4000U)
610 csd->flags |= SD_CSD_READ_BLK_PARTIAL_FLAG;
611 if (raw_csd[2U] & 0x2000U)
612 csd->flags |= SD_CSD_READ_BLK_MISALIGN_FLAG;
613 if (raw_csd[2U] & 0x1000U)
614 csd->flags |= SD_CSD_DSR_IMPLEMENTED_FLAG;
615
616 switch (csd->csd_structure) {
617 case 0:
618 csd->device_size = (uint32_t)((raw_csd[2U] &
619 0x3FFU) << 2U);
620 csd->device_size |= (uint32_t)((raw_csd[1U] &
621 0xC0000000U) >> 30U);
622 csd->read_current_min = (uint8_t)((raw_csd[1U] &
623 0x38000000U) >> 27U);
624 csd->read_current_max = (uint8_t)((raw_csd[1U] &
625 0x7000000U) >> 24U);
626 csd->write_current_min = (uint8_t)((raw_csd[1U] &
627 0xE00000U) >> 20U);
628 csd->write_current_max = (uint8_t)((raw_csd[1U] &
629 0x1C0000U) >> 18U);
630 csd->dev_size_mul = (uint8_t)((raw_csd[1U] &
631 0x38000U) >> 15U);
632
633 /* Get card total block count and block size. */
634 tmp_blk_cout = ((csd->device_size + 1U) <<
635 (csd->dev_size_mul + 2U));
636 tmp_blk_size = (1U << (csd->read_blk_len));
637 if (tmp_blk_size != SDMMC_DEFAULT_BLOCK_SIZE) {
638 tmp_blk_cout = (tmp_blk_cout * tmp_blk_size);
639 tmp_blk_size = SDMMC_DEFAULT_BLOCK_SIZE;
640 tmp_blk_cout = (tmp_blk_cout / tmp_blk_size);
641 }
642 if (blk_cout)
643 *blk_cout = tmp_blk_cout;
644 if (blk_size)
645 *blk_size = tmp_blk_size;
646 break;
647 case 1:
648 tmp_blk_size = SDMMC_DEFAULT_BLOCK_SIZE;
649
650 csd->device_size = (uint32_t)((raw_csd[2U] &
651 0x3FU) << 16U);
652 csd->device_size |= (uint32_t)((raw_csd[1U] &
653 0xFFFF0000U) >> 16U);
654
655 tmp_blk_cout = ((csd->device_size + 1U) * 1024U);
656 if (blk_cout)
657 *blk_cout = tmp_blk_cout;
658 if (blk_size)
659 *blk_size = tmp_blk_size;
660 break;
661 default:
662 break;
663 }
664
665 if ((uint8_t)((raw_csd[1U] & 0x4000U) >> 14U))
666 csd->flags |= SD_CSD_ERASE_BLK_EN_FLAG;
667 csd->erase_size = (uint8_t)((raw_csd[1U] &
668 0x3F80U) >> 7U);
669 csd->write_prtect_size = (uint8_t)(raw_csd[1U] &
670 0x7FU);
671 csd->write_speed_factor = (uint8_t)((raw_csd[0U] &
672 0x1C000000U) >> 26U);
673 csd->write_blk_len = (uint8_t)((raw_csd[0U] &
674 0x3C00000U) >> 22U);
675 if ((uint8_t)((raw_csd[0U] & 0x200000U) >> 21U))
676 csd->flags |= SD_CSD_WRITE_BLK_PARTIAL_FLAG;
677 if ((uint8_t)((raw_csd[0U] & 0x8000U) >> 15U))
678 csd->flags |= SD_CSD_FILE_FMT_GRP_FLAG;
679 if ((uint8_t)((raw_csd[0U] & 0x4000U) >> 14U))
680 csd->flags |= SD_CSD_COPY_FLAG;
681 if ((uint8_t)((raw_csd[0U] & 0x2000U) >> 13U))
682 csd->flags |=
683 SD_CSD_PERMANENT_WRITE_PROTECT_FLAG;
684 if ((uint8_t)((raw_csd[0U] & 0x1000U) >> 12U))
685 csd->flags |=
686 SD_CSD_TMP_WRITE_PROTECT_FLAG;
687 csd->file_fmt = (uint8_t)((raw_csd[0U] & 0xC00U) >> 10U);
688 }
689
sdhc_decode_scr(struct sd_scr * scr,uint32_t * raw_scr,uint32_t * version)690 static inline void sdhc_decode_scr(struct sd_scr *scr,
691 uint32_t *raw_scr, uint32_t *version)
692 {
693 uint32_t tmp_version = 0;
694
695 scr->scr_structure = (uint8_t)((raw_scr[0U] & 0xF0000000U) >> 28U);
696 scr->sd_spec = (uint8_t)((raw_scr[0U] & 0xF000000U) >> 24U);
697 if ((uint8_t)((raw_scr[0U] & 0x800000U) >> 23U))
698 scr->flags |= SD_SCR_DATA_STATUS_AFTER_ERASE;
699 scr->sd_sec = (uint8_t)((raw_scr[0U] & 0x700000U) >> 20U);
700 scr->sd_width = (uint8_t)((raw_scr[0U] & 0xF0000U) >> 16U);
701 if ((uint8_t)((raw_scr[0U] & 0x8000U) >> 15U))
702 scr->flags |= SD_SCR_SPEC3;
703 scr->sd_ext_sec = (uint8_t)((raw_scr[0U] & 0x7800U) >> 10U);
704 scr->cmd_support = (uint8_t)(raw_scr[0U] & 0x3U);
705 scr->rsvd = raw_scr[1U];
706 /* Get specification version. */
707 switch (scr->sd_spec) {
708 case 0U:
709 tmp_version = SD_SPEC_VER1_0;
710 break;
711 case 1U:
712 tmp_version = SD_SPEC_VER1_1;
713 break;
714 case 2U:
715 tmp_version = SD_SPEC_VER2_0;
716 if (scr->flags & SD_SCR_SPEC3) {
717 tmp_version = SD_SPEC_VER3_0;
718 }
719 break;
720 default:
721 break;
722 }
723
724 if (version && tmp_version)
725 *version = tmp_version;
726 }
727
sdhc_decode_cid(struct sd_cid * cid,uint32_t * raw_cid)728 static inline void sdhc_decode_cid(struct sd_cid *cid,
729 uint32_t *raw_cid)
730 {
731 cid->manufacturer = (uint8_t)((raw_cid[3U] & 0xFF000000U) >> 24U);
732 cid->application = (uint16_t)((raw_cid[3U] & 0xFFFF00U) >> 8U);
733
734 cid->name[0U] = (uint8_t)((raw_cid[3U] & 0xFFU));
735 cid->name[1U] = (uint8_t)((raw_cid[2U] & 0xFF000000U) >> 24U);
736 cid->name[2U] = (uint8_t)((raw_cid[2U] & 0xFF0000U) >> 16U);
737 cid->name[3U] = (uint8_t)((raw_cid[2U] & 0xFF00U) >> 8U);
738 cid->name[4U] = (uint8_t)((raw_cid[2U] & 0xFFU));
739
740 cid->version = (uint8_t)((raw_cid[1U] & 0xFF000000U) >> 24U);
741
742 cid->ser_num = (uint32_t)((raw_cid[1U] & 0xFFFFFFU) << 8U);
743 cid->ser_num |= (uint32_t)((raw_cid[0U] & 0xFF000000U) >> 24U);
744
745 cid->date = (uint16_t)((raw_cid[0U] & 0xFFF00U) >> 8U);
746 }
747
748 #endif /*ZEPHYR_INCLUDE_DISK_DRIVER_SDMMC_H_*/
749
