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Searched refs:ring (Results 1 – 25 of 49) sorted by relevance

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/Zephyr-Core-3.6.0/drivers/dma/
Ddma_iproc_pax_v1.c31 static inline uint32_t reset_pkt_id(struct dma_iproc_pax_ring_data *ring) in reset_pkt_id() argument
33 return ring->pkt_id = 0x0; in reset_pkt_id()
39 static inline uint32_t alloc_pkt_id(struct dma_iproc_pax_ring_data *ring) in alloc_pkt_id() argument
41 ring->pkt_id = (ring->pkt_id + 1) % 32; in alloc_pkt_id()
42 return ring->pkt_id; in alloc_pkt_id()
45 static inline uint32_t curr_pkt_id(struct dma_iproc_pax_ring_data *ring) in curr_pkt_id() argument
47 return ring->pkt_id; in curr_pkt_id()
50 static inline uint32_t curr_toggle_val(struct dma_iproc_pax_ring_data *ring) in curr_toggle_val() argument
52 return ring->curr.toggle; in curr_toggle_val()
145 static void *next_desc_addr(struct dma_iproc_pax_ring_data *ring) in next_desc_addr() argument
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Ddma_iproc_pax_v2.c34 static inline uint32_t reset_pkt_id(struct dma_iproc_pax_ring_data *ring) in reset_pkt_id() argument
36 return ring->pkt_id = 0x0; in reset_pkt_id()
39 static inline uint32_t alloc_pkt_id(struct dma_iproc_pax_ring_data *ring) in alloc_pkt_id() argument
41 ring->pkt_id = (ring->pkt_id + 1) % 32; in alloc_pkt_id()
42 return ring->pkt_id; in alloc_pkt_id()
45 static inline uint32_t curr_pkt_id(struct dma_iproc_pax_ring_data *ring) in curr_pkt_id() argument
47 return ring->pkt_id; in curr_pkt_id()
50 static inline uint32_t curr_toggle_val(struct dma_iproc_pax_ring_data *ring) in curr_toggle_val() argument
52 return ring->curr.toggle; in curr_toggle_val()
149 static inline void *get_curr_desc_addr(struct dma_iproc_pax_ring_data *ring) in get_curr_desc_addr() argument
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DKconfig.iproc_pax46 signalled from ring interrupt handler.
57 PAX DMA hardware ring operation in toggle mode
62 PAX DMA hardware ring operation in doorbell mode
Ddma_iproc_pax.h367 ((_pd)->ring[_r].ring_base + (_write_ptr))
439 uint32_t ring:2; member
506 struct dma_iproc_pax_ring_data ring[PAX_DMA_RINGS_MAX]; member
/Zephyr-Core-3.6.0/arch/xtensa/include/
Dxtensa_mmu_priv.h44 #define XTENSA_MMU_PTE(paddr, ring, attr) \ argument
46 (((ring) << XTENSA_MMU_PTE_RING_SHIFT) & XTENSA_MMU_PTE_RING_MASK) | \
59 #define XTENSA_MMU_PTE(paddr, ring, attr) \ argument
61 (((ring) << XTENSA_MMU_PTE_RING_SHIFT) & XTENSA_MMU_PTE_RING_MASK) | \
73 #define XTENSA_MMU_PTE_RING_SET(pte, ring) \ argument
75 ((ring) << XTENSA_MMU_PTE_RING_SHIFT))
182 #define XTENSA_MMU_RASID_ASID_GET(rasid, ring) \ argument
183 (((rasid) >> ((ring) * 8)) & 0xff)
215 static ALWAYS_INLINE void xtensa_rasid_asid_set(uint8_t asid, uint8_t ring) in xtensa_rasid_asid_set() argument
219 rasid = (rasid & ~(0xff << (ring * 8))) | ((uint32_t)asid << (ring * 8)); in xtensa_rasid_asid_set()
/Zephyr-Core-3.6.0/doc/kernel/data_structures/
Dring_buffers.rst6 A :dfn:`ring buffer` is a circular buffer, whose contents are stored in
19 can be enqueued and dequeued from the ring buffer in
25 legal to mix these two modes on a single ring buffer instance. A ring
38 Any number of ring buffers can be defined (limited only by available RAM). Each
39 ring buffer is referenced by its memory address.
41 A ring buffer has the following key properties:
44 bytes or 32-bit words that have been added to the ring buffer but not yet
48 the maximum amount of data (including possible metadata values) the ring
51 A ring buffer must be initialized before it can be used. This sets its
58 buffer passed change (either bytes or words) depending on how the ring
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Dindex.rst9 data, and a ring buffer for managing "byte stream" data in a clean
/Zephyr-Core-3.6.0/include/zephyr/xen/public/io/
Dconsole.h34 #define MASK_XENCONS_IDX(idx, ring) ((idx) & (sizeof(ring)-1)) argument
/Zephyr-Core-3.6.0/doc/kernel/services/data_passing/
Dpipes.rst17 The pipe can be configured with a ring buffer which holds data that has been
18 sent but not yet received; alternatively, the pipe may have no ring buffer.
25 * A **size** that indicates the size of the pipe's ring buffer. Note that a
26 size of zero defines a pipe with no ring buffer.
34 completed later. Accepted data is either copied to the pipe's ring buffer
41 data is either copied from the pipe's ring buffer or directly from the
45 either on the entire pipe or on only its ring buffer. Flushing the entire pipe
46 is equivalent to reading all the information in the ring buffer **and** waiting
48 the ring buffer is equivalent to reading **only** the data in the ring buffer
49 into a temporary buffer which is then discarded. Flushing the ring buffer does
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Dmessage_queues.rst22 * A **ring buffer** of data items that have been sent but not yet received.
26 * A **maximum quantity** of data items that can be queued in the ring buffer.
29 This sets its ring buffer to empty.
33 if one exists; otherwise the item is copied to the message queue's ring buffer,
37 If a thread attempts to send a data item when the ring buffer is full,
39 Any number of sending threads may wait simultaneously when the ring buffer
47 If a thread attempts to receive a data item when the ring buffer is empty,
49 Any number of receiving threads may wait simultaneously when the ring buffer
63 Alignment of the message queue's ring buffer is not necessary.
/Zephyr-Core-3.6.0/drivers/ethernet/
DKconfig.nxp_s32_netc39 int "TX ring length"
43 Length of the TX ring. The value must be a multiple of 8.
46 int "TX ring data buffer size"
54 int "RX ring length"
58 Length of the RX ring. The value must be a multiple of 8.
61 int "RX ring data buffer size"
DKconfig.nxp_s32_gmac16 int "TX ring length"
20 Length of the TX ring. ETH_NXP_S32_TX_RING_BUF_SIZE * ETH_NXP_S32_TX_RING_LEN
24 int "TX ring data buffer size"
33 int "RX ring length"
37 Length of the RX ring. ETH_NXP_S32_RX_RING_BUF_SIZE * ETH_NXP_S32_RX_RING_LEN
41 int "RX ring data buffer size"
Deth_ivshmem_queue.c141 q->tx.vring.avail->ring[q->tx.avail_idx % q->desc_max_len] = desc_head; in eth_ivshmem_queue_tx_commit_buff()
143 VRING_FLUSH(q->tx.vring.avail->ring[q->tx.avail_idx % q->desc_max_len]); in eth_ivshmem_queue_tx_commit_buff()
199 q->rx.vring.used->ring[used_idx].id = avail_desc_idx; in eth_ivshmem_queue_rx_complete()
200 q->rx.vring.used->ring[used_idx].len = 1; in eth_ivshmem_queue_rx_complete()
201 VRING_FLUSH(q->rx.vring.used->ring[used_idx]); in eth_ivshmem_queue_rx_complete()
274 struct vring_used_elem *used = &q->tx.vring.used->ring[ in tx_clean_used()
317 VRING_INVALIDATE(q->rx.vring.avail->ring[q->rx.avail_idx % q->desc_max_len]); in get_rx_avail_desc_idx()
318 *avail_desc_idx = q->rx.vring.avail->ring[q->rx.avail_idx % q->desc_max_len]; in get_rx_avail_desc_idx()
DKconfig.cyclonev14 int "Number of entries in the transmit descriptor ring"
27 int "Number of entries in the receive descriptor ring"
Deth_nxp_s32_netc_priv.h52 static Netc_Eth_Ip_##prefix1##BDRType nxp_s32_eth##n##_##prefix2##ring##idx##_desc[len] \
54 static uint8_t nxp_s32_eth##n##_##prefix2##ring##idx##_buf[len * buf_size] \
DKconfig.dwmac42 int "Number of entries in the transmit descriptor ring"
55 int "Number of entries in the receive descriptor ring"
Deth_nxp_s32_netc_vsi.c94 static void nxp_s32_eth##n##_rx_callback(const uint8_t unused, const uint8_t ring) \
100 if (ring == cfg->rx_ring_idx) { \
/Zephyr-Core-3.6.0/arch/xtensa/core/
Dptables.c827 size_t size, uint32_t ring, uint32_t flags) in region_map_update() argument
843 pte = XTENSA_MMU_PTE_RING_SET(l2_table[l2_pos], ring); in region_map_update()
857 size_t size, uint32_t ring, uint32_t flags, in update_region() argument
880 ret = region_map_update(ptables, va, size, ring, new_flags); in update_region()
883 ret = region_map_update(ptables, va_uc, size, ring, new_flags_uc); in update_region()
886 ret = region_map_update(ptables, start, size, ring, flags); in update_region()
937 uint32_t ring = K_MEM_PARTITION_IS_USER(partition->attr) ? XTENSA_MMU_USER_RING : in arch_mem_domain_partition_add() local
941 partition->size, ring, partition->attr, 0); in arch_mem_domain_partition_add()
1028 static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool write) in page_validate() argument
1055 if (ring > asid_ring) { in page_validate()
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DREADME_MMU.txt27 cacheability, access control based on ring (i.e. the contents of the
34 their ring field of the PTE that loaded them, via a simple translation
36 non-kernel address space will get a separate ring 3 ASID set in RASID,
38 value of ring zero is fixed at 1, it may not be changed. (An ASID
51 On a TLB miss, the hardware immediately does a single fetch (at ring 0
152 (i.e. the fixed ring zero / kernel ASID), writable, executable, and
221 stored at ASID 1 (ring 0), they can't change when the page tables
/Zephyr-Core-3.6.0/drivers/clock_control/
DKconfig.rpi_pico14 bool "Use measured frequency for ring oscillator"
/Zephyr-Core-3.6.0/subsys/usb/device/class/
DKconfig.cdc22 int "USB CDC ACM ring buffer size"
25 USB CDC ACM ring buffer size
/Zephyr-Core-3.6.0/lib/utils/
DKconfig15 Enable usage of ring buffers. This is similar to kernel FIFOs but ring
/Zephyr-Core-3.6.0/drivers/serial/
DKconfig.xen15 Enable Xen ring buffer based hypervisor console driver. Used
/Zephyr-Core-3.6.0/drivers/espi/
DKconfig.npcx54 int "Debug Port80 ring buffer size"
58 The size of the ring buffer in byte used by the Port80 ISR to store
/Zephyr-Core-3.6.0/subsys/shell/backends/
DKconfig.backends80 int "Set TX ring buffer size"
84 If UART is utilizing DMA transfers then increasing ring buffer size
88 int "Set RX ring buffer size"
93 RX ring buffer size impacts accepted latency of handling incoming
95 usually enough if ring buffer is few bytes (more than one due to

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