region_size (reference) in projects: Zephyr-Core-3.6.0

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Searched refs:region_size (Results 1 – 11 of 11) sorted by relevance

/Zephyr-Core-3.6.0/soc/arm/renesas_smartbond/da1469x/
D	soc.c	45 uint32_t region_size; in z_renesas_configure_cache() local 54 region_size = (uint32_t)&__rom_region_end - cache_start; in z_renesas_configure_cache() 65 if (region_size > MB(16)) { in z_renesas_configure_cache() 67 } else if (region_size > MB(8)) { in z_renesas_configure_cache() 69 } else if (region_size > MB(4)) { in z_renesas_configure_cache() 71 } else if (region_size > MB(2)) { in z_renesas_configure_cache() 73 } else if (region_size > MB(1)) { in z_renesas_configure_cache() 75 } else if (region_size > KB(512)) { in z_renesas_configure_cache() 77 } else if (region_size > KB(256)) { in z_renesas_configure_cache()
/Zephyr-Core-3.6.0/tests/application_development/code_relocation/
D	linker_xtensa_qemu_sram2.ld	`26 #define MPU_ALIGN(region_size) \ argument`
/Zephyr-Core-3.6.0/soc/riscv/andes_v5/ae350/
D	linker.ld	`63 #define MPU_ALIGN(region_size) \ argument 65 . = ALIGN( 1 << LOG2CEIL(region_size)) 67 #define MPU_ALIGN(region_size) \ argument 72 #define MPU_ALIGN(region_size) . = ALIGN(4) argument 205 #define MPU_ALIGN(region_size) \ argument 207 . = ALIGN( 1 << LOG2CEIL(region_size))`
/Zephyr-Core-3.6.0/include/zephyr/arch/arc/v2/
D	linker.ld	`42 #define MPU_ALIGN(region_size) \ argument 44 . = ALIGN( 1 << LOG2CEIL(region_size)) 46 #define MPU_ALIGN(region_size) \ argument 51 #define MPU_ALIGN(region_size) . = ALIGN(4) argument`
/Zephyr-Core-3.6.0/include/zephyr/arch/riscv/common/
D	linker.ld	`87 #define MPU_ALIGN(region_size) \ argument 89 . = ALIGN( 1 << LOG2CEIL(region_size)) 91 #define MPU_ALIGN(region_size) \ argument 96 #define MPU_ALIGN(region_size) . = ALIGN(4) argument`
/Zephyr-Core-3.6.0/soc/riscv/ite_ec/it8xxx2/
D	linker.ld	`56 #define MPU_ALIGN(region_size) \ argument 58 . = ALIGN( 1 << LOG2CEIL(region_size)) 60 #define MPU_ALIGN(region_size) \ argument 65 #define MPU_ALIGN(region_size) . = ALIGN(4) argument`
/Zephyr-Core-3.6.0/drivers/flash/
D	flash_npcx_fiu_nor.c	`64 size_t region_size) in is_within_region() argument 67 (addr < (region_start + region_size)) && in is_within_region() 68 ((addr + size) <= (region_start + region_size))); in is_within_region()`
/Zephyr-Core-3.6.0/include/zephyr/arch/arm/cortex_a_r/scripts/
D	linker.ld	`74 #define MPU_ALIGN(region_size) \ argument 76 . = ALIGN(1 << LOG2CEIL(region_size)) 78 #define MPU_ALIGN(region_size) \ argument`
/Zephyr-Core-3.6.0/samples/boards/intel_adsp/code_relocation/
D	linker_xtensa_intel_adsp_cavs.ld	`49 #define MPU_ALIGN(region_size) \ argument`
/Zephyr-Core-3.6.0/include/zephyr/arch/arm/cortex_m/scripts/
D	linker.ld	`76 #define MPU_ALIGN(region_size) \ argument 78 . = ALIGN( 1 << LOG2CEIL(region_size)) 80 #define MPU_ALIGN(region_size) \ argument`
/Zephyr-Core-3.6.0/arch/x86/
D	gen_mmu.py	`504 region_size = region_end - region_start 511 self.map(region_start_phys, region_start, region_size, flags, level)`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
canopennode-2.7.6
canopennode-3.5.0-3.4.0
chre-3.4.0
civetweb-2.7.6
cmsis-2.7.6
cmsis-3.4.0
cmsis-3.5.0
cmsis-3.7.0-3.6.0
cmsis-dsp-3.5.0
cmsis-dsp-3.7.0-3.6.0
cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
edtt-2.7.6
edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
fatfs-3.7.0-3.6.0-3.5.0-3.4.0
hal_adi-3.7.0
hal_altera-2.7.6
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hal_intel-3.5.0
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hal_microchip-2.7.6
hal_microchip-3.6.0-3.5.0-3.4.0
hal_microchip-3.7.0
hal_nordic-2.7.6
hal_nordic-3.4.0
hal_nordic-3.5.0
hal_nordic-3.6.0
hal_nordic-3.7.0
hal_nuvoton-2.7.6
hal_nuvoton-3.4.0
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hal_nuvoton-3.6.0
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hal_nxp-2.7.6
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hal_openisa-2.7.6
hal_openisa-3.5.0-3.4.0
hal_openisa-3.7.0-3.6.0
hal_quicklogic-3.6.0-3.5.0-3.4.0-2.7.6
hal_quicklogic-3.7.0
hal_renesas-3.4.0
hal_renesas-3.5.0
hal_renesas-3.6.0
hal_renesas-3.7.0
hal_rpi_pico-3.4.0
hal_rpi_pico-3.7.0-3.6.0-3.5.0
hal_silabs-2.7.6
hal_silabs-3.4.0
hal_silabs-3.5.0
hal_silabs-3.6.0
hal_silabs-3.7.0
hal_st-2.7.6
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hal_st-3.6.0
hal_st-3.7.0
hal_stm32-2.7.6
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hal_stm32-3.6.0
hal_stm32-3.7.0
hal_telink-2.7.6
hal_telink-3.6.0-3.5.0-3.4.0
hal_telink-3.7.0
hal_ti-2.7.6
hal_ti-3.4.0
hal_ti-3.7.0-3.6.0-3.5.0
hal_wurthelektronik-3.5.0-3.4.0
hal_wurthelektronik-3.7.0-3.6.0
hal_xtensa-2.7.6
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libmetal-3.7.0
littlefs-2.7.6
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loramac-node-2.7.6
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loramac-node-3.6.0-3.5.0
loramac-node-3.7.0
lvgl-2.7.6
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lz4-3.4.0-2.7.6
mbedtls-2.7.6
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mcuboot-2.7.6
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mcuboot-3.5.0
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mcuboot-3.7.0
mcumgr-2.7.6
mipi-sys-t-2.7.6
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nanopb-2.7.6
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net-tools-2.7.6
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nrf_hw_models-2.7.6
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psa-arch-tests-3.4.0
segger-2.7.6
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segger-3.7.0
sof-2.7.6
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tf-m-tests-3.4.0
tflite-micro-3.4.0-2.7.6
thrift-3.4.0
tinycbor-2.7.6
tinycrypt-3.6.0-3.5.0-3.4.0-2.7.6
tinycrypt-3.7.0
trusted-firmware-a-3.4.0
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uoscore-uedhoc-3.4.0
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zcbor-3.5.0-3.4.0
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zscilib-3.4.0