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Searched refs:pllr (Results 1 – 5 of 5) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32g4.c68 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32g0.c64 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32l4_l5_wb_wl.c83 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32_ll_common.h28 #define pllr(v) z_pllr(v) macro
Dclock_stm32f2_f4_f7.c60 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()