| /Zephyr-Core-3.6.0/drivers/pcie/host/ |
| D | msi.c | 13 static uint32_t pcie_msi_base(pcie_bdf_t bdf, bool *msi) in pcie_msi_base() argument
17 if (msi != NULL) { in pcie_msi_base()
18 *msi = true; in pcie_msi_base()
30 if (msi != NULL) { in pcie_msi_base()
31 *msi = false; in pcie_msi_base()
146 bool msi; in pcie_msi_vectors_allocate() local
148 base = pcie_msi_base(bdf, &msi); in pcie_msi_vectors_allocate()
151 set_msix(vectors, n_vector, !msi); in pcie_msi_vectors_allocate()
153 if (!msi) { in pcie_msi_vectors_allocate()
162 if (msi) { in pcie_msi_vectors_allocate()
[all …]
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| D | shell.c | 96 uint32_t msi; in show_msi() local
99 msi = pcie_get_cap(bdf, PCI_CAP_ID_MSI); in show_msi()
101 if (msi) { in show_msi()
102 data = pcie_conf_read(bdf, msi + PCIE_MSI_MCR); in show_msi()
109 msi = pcie_get_cap(bdf, PCI_CAP_ID_MSIX); in show_msi()
111 if (msi) { in show_msi()
115 data = pcie_conf_read(bdf, msi + PCIE_MSIX_MCR); in show_msi()
126 offset = pcie_conf_read(bdf, msi + PCIE_MSIX_TR); in show_msi()
134 offset = pcie_conf_read(bdf, msi + PCIE_MSIX_PBA); in show_msi()
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| D | CMakeLists.txt | 6 zephyr_library_sources_ifdef(CONFIG_PCIE_MSI msi.c)
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| /Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/ |
| D | core_init.overlay | 33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
78 msi-range = <4>;
79 msi-pll-mode;
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| D | spi1_msik.overlay | 13 msi-range = <4>;
14 msi-pll-mode;
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| /Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | clear_msi.overlay | 8 * Warning: This overlay clears the msi clock back to a state equivalent to what could
14 /delete-property/ msi-range;
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| D | pll_48_msi_4.overlay | 10 * It applies to the stm32xx where the msi is 4MHz
15 msi-range = <6>; /* default value */
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| D | wb_pll_48_msi_4.overlay | 10 * It applies to the stm32wb where the msi is 4MHz
15 msi-range = <6>; /* default value */
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| D | msi_range6.overlay | 14 msi-range = <6>;
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| D | msi_range11.overlay | 14 msi-range = <11>;
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| /Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/ |
| D | msis_24.overlay | 18 msi-range = <1>;
19 msi-pll-mode;
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| D | msis_48.overlay | 18 msi-range = <0>;
19 msi-pll-mode;
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| D | pll_msis_160.overlay | 18 msi-range = <4>;
19 msi-pll-mode;
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| D | pll_msis_ahb_2_40.overlay | 18 msi-range = <4>;
19 msi-pll-mode;
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| D | clear_clocks.overlay | 28 /delete-property/ msi-range;
29 /delete-property/ msi-pll-mode;
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| /Zephyr-Core-3.6.0/include/zephyr/drivers/interrupt_controller/ |
| D | intel_vtd.h | 43 bool msi);
213 bool msi) in vtd_set_irte_msi() argument
218 return api->set_irte_msi(dev, irte_idx, msi); in vtd_set_irte_msi()
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| /Zephyr-Core-3.6.0/boards/arm/nucleo_u575zi_q/ |
| D | nucleo_u575zi_q-common.dtsi | 64 msi-range = <4>;
65 msi-pll-mode;
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| /Zephyr-Core-3.6.0/boards/arm/nucleo_u5a5zj_q/ |
| D | nucleo_u5a5zj_q-common.dtsi | 64 msi-range = <4>;
65 msi-pll-mode;
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| /Zephyr-Core-3.6.0/boards/arm/b_u585i_iot02a/ |
| D | b_u585i_iot02a-common.dtsi | 54 msi-range = <4>;
55 msi-pll-mode;
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| /Zephyr-Core-3.6.0/drivers/interrupt_controller/ |
| D | intc_intel_vtd.c | 454 uint8_t irte_idx, bool msi) in vtd_ictl_set_irte_msi() argument
458 data->msi[irte_idx] = msi; in vtd_ictl_set_irte_msi()
466 return data->msi[irte_idx]; in vtd_ictl_irte_is_msi()
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| /Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | wb_i2c1_hsi_lptim1_lse.overlay | 26 /delete-property/ msi-range;
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| D | wb_i2c1_sysclk_lptim1_lsi.overlay | 26 /delete-property/ msi-range;
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| /Zephyr-Core-3.6.0/dts/arm64/qemu/ |
| D | qemu-virt-a53.dtsi | 81 msi-controller;
150 msi-parent = <&its>;
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| D | qemu-virt-arm64.dtsi | 81 msi-controller;
150 msi-parent = <&its>;
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| /Zephyr-Core-3.6.0/boards/arm/stm32l562e_dk/ |
| D | stm32l562e_dk_common.dtsi | 48 msi-range = <6>;
49 msi-pll-mode;
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