mainpll_addr (reference) in projects: Zephyr-Core-3.6.0

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/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_control_agilex5_ll.c	18 mm_reg_t mainpll_addr; member 33 clock_agilex5_ll.mainpll_addr = clock_agilex5_ll.base_addr + CLKMGR_MAINPLL_OFFSET; in clock_agilex5_ll_init() 87 clk_psrc = sys_read32(clock_agilex5_ll.mainpll_addr + psrc_reg); in get_clk_freq() 91 pllm_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLM; in get_clk_freq() 92 pllc_reg = clock_agilex5_ll.mainpll_addr + main_pllc; in get_clk_freq() 93 pllglob_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLGLOB; in get_clk_freq() 151 mainpll_nocdiv = sys_read32(clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_NOCDIV); in get_uart_clk()

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
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