1 /* 2 * Copyright (c) 2020, Seagate Technology LLC 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_LPC11U6X_H_ 8 #define ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_LPC11U6X_H_ 9 10 #include <zephyr/drivers/pinctrl.h> 11 12 #define LPC11U6X_SYS_AHB_CLK_CTRL_I2C0 (1 << 5) 13 #define LPC11U6X_SYS_AHB_CLK_CTRL_GPIO (1 << 6) 14 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART0 (1 << 12) 15 #define LPC11U6X_SYS_AHB_CLK_CTRL_USB (1 << 14) 16 #define LPC11U6X_SYS_AHB_CLK_CTRL_IOCON (1 << 16) 17 #define LPC11U6X_SYS_AHB_CLK_CTRL_PINT (1 << 19) 18 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART1 (1 << 20) 19 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART2 (1 << 21) 20 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART3_4 (1 << 22) 21 #define LPC11U6X_SYS_AHB_CLK_CTRL_I2C1 (1 << 25) 22 #define LPC11U6X_SYS_AHB_CLK_CTRL_SRAM1 (1 << 26) 23 #define LPC11U6X_SYS_AHB_CLK_CTRL_USB_SRAM (1 << 27) 24 25 #define LPC11U6X_PDRUNCFG_IRC_PD (1 << 1) 26 #define LPC11U6X_PDRUNCFG_SYSOSC_PD (1 << 5) 27 #define LPC11U6X_PDRUNCFG_PLL_PD (1 << 7) 28 #define LPC11U6X_PDRUNCFG_MASK 0xC800 29 30 #define LPC11U6X_SYS_PLL_CLK_SEL_IRC 0x0 31 #define LPC11U6X_SYS_PLL_CLK_SEL_SYSOSC 0x1 32 33 #define LPC11U6X_FLASH_TIMING_REG 0x4003C010 34 #define LPC11U6X_FLASH_TIMING_3CYCLES 0x2 35 #define LPC11U6X_FLASH_TIMING_MASK 0x3 36 37 #define LPC11U6X_SYS_PLL_CTRL_MSEL_MASK 0x1F 38 #define LPC11U6X_SYS_PLL_CTRL_PSEL_SHIFT 5 39 #define LPC11U6X_SYS_PLL_CTRL_PSEL_MASK 0x3 40 41 #define LPC11U6X_MAIN_CLK_SRC_PLLOUT 0x3 42 43 #define LPC11U6X_PRESET_CTRL_I2C0 (1 << 1) 44 #define LPC11U6X_PRESET_CTRL_I2C1 (1 << 3) 45 #define LPC11U6X_PRESET_CTRL_FRG (1 << 4) 46 #define LPC11U6X_PRESET_CTRL_USART1 (1 << 5) 47 #define LPC11U6X_PRESET_CTRL_USART2 (1 << 6) 48 #define LPC11U6X_PRESET_CTRL_USART3 (1 << 7) 49 #define LPC11U6X_PRESET_CTRL_USART4 (1 << 8) 50 51 #define LPC11U6X_USART_CLOCK_RATE 14745600 52 53 struct lpc11u6x_syscon_regs { 54 volatile uint32_t sys_mem_remap; /* System memory remap */ 55 volatile uint32_t p_reset_ctrl; /* Peripheral reset control */ 56 volatile uint32_t sys_pll_ctrl; /* System PLL control */ 57 volatile const uint32_t sys_pll_stat; /* System PLL status */ 58 volatile uint32_t usb_pll_ctrl; /* USB PLL control */ 59 volatile const uint32_t usb_pll_stat; /* USB PLL status */ 60 volatile const uint32_t reserved1; 61 volatile uint32_t rtc_osc_ctrl; /* RTC oscillator control */ 62 volatile uint32_t sys_osc_ctrl; /* System oscillator control */ 63 volatile uint32_t wdt_osc_ctrl; /* Watchdog oscillator 64 * control 65 */ 66 volatile uint32_t irc_ctrl; /* IRC Control */ 67 volatile const uint32_t reserved2; 68 volatile uint32_t sys_rst_stat; /* System reset status */ 69 volatile const uint32_t reserved3[3]; 70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */ 71 volatile uint32_t sys_pll_clk_uen; /* System PLL source update */ 72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */ 73 volatile uint32_t usb_pll_clk_uen; /* USB PLL clock source 74 * update 75 */ 76 volatile const uint32_t reserved4[8]; 77 volatile uint32_t main_clk_sel; /* Main clock select */ 78 volatile uint32_t main_clk_uen; /* Main clock update */ 79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */ 80 volatile const uint32_t reserved5; 81 volatile uint32_t sys_ahb_clk_ctrl; /* System clock control */ 82 volatile const uint32_t reserved6[4]; 83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */ 84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */ 85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */ 86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud 87 * rate generator clock divider 88 */ 89 volatile const uint32_t reserved7[7]; 90 volatile uint32_t usb_clk_sel; /* USB clock select */ 91 volatile uint32_t usb_clk_uen; /* USB clock update */ 92 volatile uint32_t usb_clk_div; /* USB clock divider */ 93 volatile const uint32_t reserved8[5]; 94 volatile uint32_t clk_out_sel; /* CLKOUT source select */ 95 volatile uint32_t clk_out_uen; /* CLKOUT source update */ 96 volatile uint32_t clk_out_div; /* CLKOUT divider */ 97 volatile const uint32_t reserved9; 98 volatile uint32_t uart_frg_div; /* USART1-4 fractional 99 * generator divider 100 */ 101 volatile uint32_t uart_frg_mult; /* USART1-4 fractional 102 * generator multiplier 103 */ 104 volatile const uint32_t reserved10; 105 volatile uint32_t ext_trace_cmd; /* External trace buffer 106 * command 107 */ 108 volatile const uint32_t pio_por_cap[3]; /* CLKOUT source select */ 109 volatile const uint32_t reserved11[10]; 110 volatile uint32_t iocon_clk_div[7]; /* IOCON clock divider */ 111 volatile uint32_t bod_ctrl; /* Brown-out detect control */ 112 volatile uint32_t sys_tck_cal; /* System tick calibration */ 113 volatile const uint32_t reserved12[6]; 114 volatile uint32_t irq_latency; /* IRQ latency */ 115 volatile uint32_t nmi_src; /* NMI source control */ 116 volatile uint32_t pint_sel[8]; /* GPIO pin interrupt select */ 117 volatile uint32_t usb_clk_ctrl; /* USB clock control */ 118 volatile const uint32_t usb_clk_stat; /* USB clock status */ 119 volatile uint32_t reserved13[25]; 120 volatile uint32_t starterp0; /* Start logic 0 int wake-up */ 121 volatile const uint32_t reserved14[3]; 122 volatile uint32_t starterp1; /* Start logic 1 int wake-up */ 123 volatile const uint32_t reserved15[6]; 124 volatile uint32_t pd_sleep_cfg; /* Deep-sleep power-down 125 * states 126 */ 127 volatile uint32_t pd_awake_cfg; /* Power-down states for 128 * wake-up from deep-sleep 129 */ 130 volatile uint32_t pd_run_cfg; /* Power configuration */ 131 volatile const uint32_t reserved16[110]; 132 volatile const uint32_t device_id; /* Device identifier */ 133 }; 134 135 struct lpc11u6x_syscon_config { 136 struct lpc11u6x_syscon_regs *syscon; 137 const struct pinctrl_dev_config *pincfg; 138 }; 139 140 struct lpc11u6x_syscon_data { 141 struct k_mutex mutex; 142 uint8_t frg_in_use; 143 uint8_t usart34_in_use; 144 }; 145 #endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_LPC11U6X_H_ */ 146
